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TC58NVG1S3ETAI0

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P65
TC58NVG1S3ETAI0
2012-09-01C
46
Multi Page Copy (2)
By using Multi Page Copy (2), data in two pages can be copied to another pages after the data has been read out.
When the each block address changes (increments) this sequenced has to be started from the beginning.
Same page address (PA0 to PA5) within two districts has to be selected.
t
R
BYRY/
60
Command
input
Address
PA0 to PA16
(Page m0 ; District 0)
Address input
30
A
00
Address input
E0 Data output
Address
CA0 to CA11, PA0 to PA16
(Page m0)
A
60
Address input
Address
PA0 to PA16
(Page n0 ; District 1)
05
Address input
Address
CA0 to CA11
(Col = 0)
t
DCBSYW1
00
Address input
05
Address input
E0
B
B
Data output
Address
CA0 to CA11, PA0 to PA16
(Page n0)
Address
CA0 to CA11
(Col = 0)
8C
Address input
11
Data input
Address
CA0 to CA11, PA0 to PA16
(Page M0 ; District 0)
BYRY/
A
A
00
Address input
05
Address input
E0
Data output
Address
CA0 to CA11, PA0 to PA16
(Page m1)
Address
CA0 to CA11
(Col = 0)
BYRY/
00
Address input
05
Address input
E0
Data output
Address
CA0 to CA11, PA0 to PA16
(Page n1)
Address
CA0 to CA11
(Col = 0)
D
D
C
C
t
DCBSYW2
8C
Address input
15
Data input
Address
CA0 to CA11, PA0 to PA16
(Page N0 ; District 1)
BYRY/
60
Address
PA0 to PA16
(Page m1 ; District 0)
Address input
3A60
Address input
Address
PA0 to PA16
(Page n1 ; District 1)
C
C
B
B
t
DCBSYR2
TC58NVG1S3ETAI0
2012-09-01C
47
t
DCBSYW1
00
Address input
05
Address input
E0
G
G
Data output
Address
CA0 to CA11, PA0 to PA16
(Page n63)
Address
CA0 to CA11
(Col = 0)
8C
Address input
11
Data input
Address
CA0 to CA11, PA0 to PA16
(Page M63 ; District 0)
BYRY/
F
F
t
DCBSYR2
BYRY/
60
Address
PA0 to PA16
(Page m63 ; District 0)
Address input
3A
F
00
Address input
E0 Data output
Address
CA0 to CA11, PA0 to PA16
(Page m63)
F
60
Address input
Address
PA0 to PA16
(Page n63 ; District 1)
05
Address input
Address
CA0 to CA11
(Col = 0)
E
E
t
DCBSYW1
8C
Address input
11
Data input
Address
CA0 to CA11, PA0 to PA16
(Page M1 ; District 0)
BYRY/
E
E
D
D
8C
Address input
15
Data input
Address
CA0 to CA11, PA0 to PA16
(Page N1 ; District 1)
t
DCBSYW2
BYRY/
G
G
8C
Address input
10
Data input
Address
CA0 to CA11, PA0 to PA16
(Page N63 ; District 1)
tPROG
(
*1
)
Note)
This operation needs to be executed within each District.
Data input is required only if previous data output needs to be altered.
If the data has to be changed, locate the desired address with the column and page address input after
the 8Ch command, and change only the data that needs be changed.
If the data does not have to be changed, data input cycles are not required.
Make sure
WP is held to High level when Multi Page Copy (2) operation is performed.
Also make sure the Multi Page Copy operation is terminated with 8Ch-10h command sequence
(
*1) t
PROG
: Since the last page programming by 10h command is initiated after the previous cache
program, the t
PROG*
during cache programming is given by the following equation.
t
PROG
= t
PROG
of the last page + t
PROG
of the previous page-A
A
= (command input cycle + address input cycle + data output/input cycle time of the last page)
If “A” exceeds the t
PROG
of previous page, t
PROG
of the last page is t
PROG
max.
TC58NVG1S3ETAI0
2012-09-01C
48
Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which
follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
Multi Block Erase
The Multi Block Erase operation starts by selecting two block addresses before D0h command as in below
diagram. The device automatically executes the Erase and Verify operations and the result can be monitored by
checking the status by 71h status read command. For details on 71h status read command, refer to section
“Multi Page Program with Data Cache”.
Internal addressing in relation with the Districts
To use Multi Block Erase operation, the internal addressing should be considered in relation with the District.
• The device consists from 2 Districts.
• Each District consists from 1024 erase blocks.
• The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
Address input restriction for the Multi Block Erase
There are following restrictions in using Multi Block Erase
(Restriction)
Maximum one block should be selected from each District.
For example;
(60) [District 0] (60) [District 1] (D0)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 1] (60) [District 0] (D0)
It requires no mutual address relation between the selected blocks from each District.
Make sure to terminate the operation with D0h command. If the operation needs to be terminated before D0h
command input, input the FFh reset command to terminate the operation.
Pass
I/O
Fail
BY/RY
60 D0 70
Block Address
input: 3 cycles
Status Read
command
Busy
Erase Start
command
Pass
I/O
Fail
BY/RY
60
D0
71
Block Address
input: 3 cycles
District 0
Status Read
command
Busy
Erase Start
command
60
Block Address
input: 3 cycles
District 1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P65

TC58NVG1S3ETAI0

Mfr. #:
Buy TC58NVG1S3ETAI0
Manufacturer:
Toshiba Memory
Description:
NAND Flash 3.3V 2Gb 43nm SLC NAND (EEPROM)
Lifecycle:
New from this manufacturer.
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