TC58NVG1S3ETAI0
2012-09-01C
25
Multi Block Erase Timing Diagram
60h
PA8
to 15
WE
CLE
CE
ALE
RE
BY/RY
: V
IH
or V
IL
t
CS
t
CLS
t
CLH
t
CLS
PA0
to 7
t
DS
t
DH
t
ALS
: Do not input data while data is being output.
D0h 71h
t
WB
t
BERASE
Busy
Status Read
command
Auto Block
Erase Setup
command
I/O1
to
Status
output
t
ALH
Repeat 2 times (District-0,1)
PA16
TC58NVG1S3ETAI0
2012-09-01C
26
ID Read Operation Timing Diagram
: V
IH
or V
IL
WE
CLE
RE
t
CEA
CE
ALE
I/O
t
AR
ID Read
command
Address
00
Maker code
Device code
t
REA
t
CLS
t
CS
t
DS
t
CH
t
ALH
t
ALS
t
CLS
t
CS
t
CH
t
ALH
t
DH
90h 00h 98h
t
REA
DAh
t
REA
t
REA
See
Table 5
See
Table 5
t
REA
See
Table 5
TC58NVG1S3ETAI0
2012-09-01C
27
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal command
register. The command is latched into the command register from the I/O port on the rising edge of the
WE
signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading address information into the internal address register. Address
information is latched into the address register from the I/O port on the rising edge of
WE while ALE is High.
Chip Enable:
The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The
CE signal is ignored when device is in Busy state ( BY/RY = L), such as during a Program or Erase or Read
operation, and will not enter Standby mode even if the
CE input goes High.
Write Enable:
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable:
The RE signal controls serial data output. Data is available t
REA
after the falling edge of RE .
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.
Write Protect:
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when
WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy:
The BY/RY output signal is used to indicate the operating condition of the device. The BY/RY signal is
in Busy state (
BY/RY = L) during the Program, Erase and Read operations and will return to Ready state
(
BY/RY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vccq with an appropriate resister.
If RY / BY signal is not pulled-up to Vccq( “Open” state ), device operation can not guarantee.
CE
WE
RE
WP
BY/RY

TC58NVG1S3ETAI0

Mfr. #:
Manufacturer:
Toshiba Memory
Description:
NAND Flash 3.3V 2Gb 43nm SLC NAND (EEPROM)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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