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Multi Page Program
The device has a Multi Page Program, which enables even higher speed program operation compared to Auto Page Program. The sequence of command, address and data
input is shown bellow. (Refer to the detailed timing chart.)
Although two planes are programmed simultaneously, pass/fail is not available for each page when the program operation completes. Status bit of I/O 0 is set to “1” when
any of the pages fails. Limitation in addressing with Multi Page Program is shown below.
Multi Page Program
NOTE: Any command between 11h and 81h is prohibited except 70h and FFh.
Data
Input
80h 11h
Plane 0
(1024 Block)
Block 0
Block 2
Block 2044
Block 2046
81h 10h
Plane 1
(1024 Block)
Block 1
Block 3
Block 2045
Block 2047
I/O0~7
R/
B
I/O0
Pass
Fail
”1”
”0”
tDCBSYW1
tPROG
CA0~CA11 : Valid
PA0~PA5 : Valid’
PA6 : District0’
PA7~PA16 : Valid’
80h
Address & Data Input 11h
CA0~CA11 : Valid
PA0~PA5 : Valid
PA6 : District1
PA7~PA16 : Valid
81h
Address & Data Input 10h 70h
Note
TC58NVG1S3ETAI0
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Auto Page Program Operation with Data Cache
The device has an Auto Page Program with Data Cache operation enabling the high speed program operation shown below. When the block address changes this
sequenced has to be started from the beginning.
BY/RY
CLE
ALE
I/O
CE
WE
Page N
80h
A
dd
A
dd
A
dd
A
dd
Status Output
Din
15h 70h
Din Din
Page N + 1
80h
A
dd
A
dd
A
dd
A
dd
1
Status Output
Din
15h 70h
Din Din
Page N + P
80h
A
dd
A
dd
A
dd
A
dd
3 4
Status Output
Din
10h 70h
Din Din
5 6
Data Cache
Page Buffer
Cell Array
Page N
+ P
1
2
3
4
5
5
6
Page N
Page N + 1
Data for Page N + P
3
A
dd
A
dd
A
dd
Data for Page N
Data for Page N
Data for Page N + 1
Data for Page N + 1
Page N + P 1
t
DCBSYW2
t
DCBSYW2
t
PROG (NOTE)
Issuing the 15h command to the device after serial data input initiates the program operation with Data Cache
1 Data for Page N is input to Data Cache.
2 Data is transferred to the Page Buffer by the 15h command. During the transfer the Ready/Busy outputs Busy State (t
DCBSYW2
).
3 Data is programmed to the selected page while the data for page N
+ 1 is input to the Data Cache.
4 By the 15h command, the data in the Data Cache is transferred to the Page Buffer after the programming of page N is completed. The device output busy state from the 15h command
until the Data Cache becomes empty. The duration of this period depends on timing between the internal programming of page N and serial data input for Page N
+ 1 (t
DCBSYW2
).
5 Data for Page N
+ P is input to the Data Cache while the data of the Page N + P 1 is being programmed.
6 The programming with Data Cache is terminated by the 10h command. When the device becomes Ready, it shows that the internal programming of the Page N
+ P is completed.
NOTE: Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG during cache programming is given by the following;
t
PROG
= t
PROG
for the last page + t
PROG
of the previous page ( command input cycle + address input cycle + data input cycle time of the previous page)
RE
2
TC58NVG1S3ETAI0
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Pass/fail status for each page programmed by the Auto Page Programming with Data Cache operation can be detected by the Status Read operation.
z I/O1 : Pass/fail of the current page program operation.
z I/O2 : Pass/fail of the previous page program operation.
The Pass/Fail status on I/O1 and I/O2 are valid under the following conditions.
z Status on I/O1: Page Buffer Ready/Busy is Ready State.
The Page Buffer Ready/Busy is output on I/O6 by Status Read operation or
BY/RY pin after the 10h command
z Status on I/O2: Data Cache Read/Busy is Ready State.
The Data Cache Ready/Busy is output on I/O7 by Status Read operation or BY/RY pin after the 15h command.
80h…15h
70h
Status
Out
Page 1
Data Cache Busy
Page Buffer Busy
Page 1
Page 2
70h
70h
Page 2
70h
80h…15h
Page N
1
80h…10h
Page N
Page N 1
Page N
70h
80h…15h
I/O2 =>
I/O1 =>
Invalid
Invalid
Page 1
Invalid
Page N 2
Invalid
invalid
invalid
Page N 1
Page N
Page 1
Page 2
70h
If the Page Buffer Busy returns to Ready before the next 80h command input, and if Status Read is done during
this Ready period, the Status Read provides pass/fail for Page 2 on I/O1 and pass/fail result for Page1 on I/O2
Status
Out
Status
Out
Status
Out
Status
Out
Status
Out
Example)
BYRY/ pin

TC58NVG1S3ETAI0

Mfr. #:
Manufacturer:
Toshiba Memory
Description:
NAND Flash 3.3V 2Gb 43nm SLC NAND (EEPROM)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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