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An application example with multiple devices is shown in the figure below.
System Design Note: If the
BY/RY pin signals from multiple devices are wired together as shown in the
diagram, the Status Read function can be used to determine the status of each individual device.
Reset
The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally
generated voltage is discharged to 0 volt and the device enters the Wait state.
Reset during a Cache Program/Page Copy may not just stop the most recent page program but it may also
stop the previous program to a page depending on when the FF reset is input.
The response to a “FFh” Reset command input during the various device operations is as follows:
When a Reset (FFh) command is input during programming
Internal V
PP
80 10 FF 00
BY/RY
t
RST
(max 10 μs)
Device
1
CLE
1CE
Device
2
2CE
Device
3
3CE
Device
N
NCE
Device
N
+ 1
1NCE +
ALE
WE
RE
BY/RY
WE
RE
Status on Device 1
70h
1CE
ALE
I/O
70h
Status on Device N
BY/RY
CLE
NCE
Busy
I/O1
to I/O8
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When a Reset (FFh) command is input during erasing
When a Reset (FFh) command is input during Read operation
When a Reset (FFh) command is input during Ready
When a Status Read command (70h) is input after a Reset
When two or more Reset commands are input in succession
10
BY/RY
FF FF
(3)(2)(1)
The second command is invalid, but the third command is valid.
FF FF
FF
I/O status : Pass/Fail Pass
: Ready/Busy
Ready
FF 70
BY/RY
00 FF 00
BY/RY
t
RST
(max 6 μs)
30
Internal erase
voltage
D0 FF 00
BY/RY
t
RST
(max 500 μs)
00
BY/RY
t
RST
(max 6 μs)
FF
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APPLICATION NOTES AND COMMENTS
(1) Power-on/off sequence:
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power on
sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the
figure below. In this time period, the acceptable commands are FFh or 70h.
The
WP signal is useful for protecting against data corruption at power-on/off.
(2) Power-on Reset
The following sequence is necessary because some input signals may not be stable at power-on.
(3) Prohibition of unspecified commands
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
(4) Restriction of commands while in the Busy state
During the Busy state, do not input any command except 70h(71h) and FFh.
V
IL
Operation
0 V
V
CC
2.7 V
2.5V
V
IL
Don’t
care
Don’t
care
V
IH
CE
, WE , RE
WP
CLE, ALE
Invalid
Don’t
care
Ready/Busy
1 ms max
100 μs max
FF
Reset
Power on

TC58NVG1S3ETAI0

Mfr. #:
Manufacturer:
Toshiba Memory
Description:
NAND Flash 3.3V 2Gb 43nm SLC NAND (EEPROM)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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