STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
IDT™
17 STAC9752/9753
REV 3.3 1206
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
2.2.3. Clocks
Figure 4. Clocks Timing
2.2.4. STAC9752/9753 Crystal Elimination Circuit and Clock Frequencies
The STAC9752/9753 supports several clock frequency inputs as described in the following table. In
general, when a 24.576 MHz crystal is not used, the XTALOUT pin should be tied to ground. This
short to ground configures the part into an alternate clock mode and enables an on board PLL.
CODEC Modes:
P = The STAC9752/9753 as a Primary CODEC.
S = The STAC9752/9753 as a Secondary CODEC.
Parameter Symbol Min Typ Max Units
BIT_CLK frequency - 12.288 - MHz
BIT_CLK period Tclk_period - 81.4 - ns
BIT_CLK output jitter - 750 - ps
BLT_CLK high pulse width (Note 1) Tclk_high 36 40.7 45 ns
BIT_CLK low pulse width (Note 1) Tclk_low 36 40.7 45 ns
SYNC frequency - 48.0 - KHz
SYNC period Tsync_period - 20.8 - µs
SYNC high pulse width Tsync_high - 1.3 - µs
SYNC low pulse width Tsync_low - 19.5 - µs
Note: 1. Worst case duty cycle restricted to 45/55.
Table 1. Clock Mode Configuration
XTL_OUT Pin Config CID1 Pin Config CID0 Pin Config Clock Source Input CODEC Mode CODEC ID
XTAL float float 24.576 MHz xtal P 0
XTAL or open float pulldown 12.288 MHz bit clk S 1
XTAL or open pulldown float 12.288 MHz bit clk S 2
XTAL or open pulldown pulldown 12.288 MHz bit clk S 3
short to ground float float 14.31818 MHz source P 0
short to ground float pulldown 27 MHz source P 0
short to ground pulldown float 48 MHz source P 0
short to ground pulldown pulldown 24.576 MHz source P 0
SYNC
BIT_CLK
Tclk_high
Tclk_low
Tclk_period
Tsync_high
Tsync_period
Tsync_low
