STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
IDT™
62 STAC9752/9753
REV 3.3 1206
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
8.1.20.1. Variable Rate Sampling Enable
The Extended Audio Status Control register also contains one active bit to enable or disable the
Variable Sampling Rate capabilities of the DACs and ADCs. If the VRA (bit D0) is 1, the variable
sample rate control registers (2Ch and 32h) are active, and “on-demand” slot data required transfers
are allowed. If the VRA bit is 0, the DACs and ADCs will operate at the default 48 KHz data rate.
The STAC9752/9753 supports “on-demand” slot request flags. These flags are passed from the
CODEC to the AC’97 controller in every audio input frame. Each time a slot request flag is set (active
low) in a given audio frame, the controller will pass the next PCM sample for the corresponding slot
in the audio frame that immediately follows. The VRA enable bit must be set to 1 to enable
“on-demand” data transfers. If the VRA enable bit is not set, the CODEC defaults to 48 KHz transfers
and every audio frame includes an active slot request flag and data transfers every frame.
For variable sample rate output, the CODEC examines its sample rate control registers, the state of
the FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to
determine which SLOTREQ bits to set active (low). SLOTREQ bits are asserted during the current
audio input frame for active output slots, which will require data in the next audio output frame.
For variable sample rate input, the tag bit for each input slot indicates whether valid data is present
or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN
(CODEC to Controller), the CODEC sets the TAG bit; for SDATA_OUT (Controller to CODEC), the
CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame. Whenever VRA is
set to 0, the PCM rate registers (2Ch and 32h) are overwritten with BB80h (48 KHz).
8.1.20.2. SPDIF
The SPDIF bit in the Extended Audio Status Control Register is used to enable and disable the
SPDIF functionality within the STAC9752/9753. If the SPDIF is set to a 1, then the function is
enabled, and when set to a 0 it is disabled.
8.1.20.3. SPCV (SPDIF Configuration Valid)
The SPCV bit is read only and indicates whether or not the SPDIF system is set up correctly. When
SPCV is a 0, it indicates the SPDIF configuration is invalid. When SPCV is a 1, it indicates the
SPDIF configuration is valid.
8.1.20.4. SPSA1, SPSA0 (SPDIF Slot Assignment)
SPSA1 and SPSA0 combine to provide the slot assignments for the SPDIF data. The following
details the slot assignment relationship between SPSA1 and SPSA0.
The STAC9752/9753 are AMAP compliant with the following table.
1 0 Reserved Bit not used, should read back 0
0 0 VRA Enable
0 = VRA Disabled, DAC and ADC set to 48 KHz (Registers 2Ch and 32h
loaded with the value BB80h)
1 = VRA Enabled, Reg. 2Ch & 32h control sample rate
Bit(s) Reset Value Name Description
