STAC9753XXTAEB2X Datasheet STAC9753XXTAEB2X, STAC9753XXTAEB2XR | P34-P36

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

34 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

5.3.1. Slot 0: TAG / CODEC ID

Table 7. Output Slot 0 Bit Definitions

Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the

entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains

at least one time slot of valid data. The next 12 bit positions sampled by AC‘97 indicate which of the

corresponding 12 time slots contain valid data. In this way data streams of differing sample rates can

be transmitted across AC-Link at its fixed 48 KHz audio frame rate.

The two LSBs of Slot 0 transmit the CODEC ID used to distinguish Primary and Secondary CODEC

5.3.2. Slot 1: Command Address Port

The command port is used to control features and monitor status (see AC-Link input frame Slots 1

and 2) for AC‘97 CODEC functions including, but not limited to, mixer settings, and power manage-

ment (refer to the control register section of this specification).

The control interface architecture supports up to 64 16-bit read/write registers, addressable on even

byte boundaries. Only the even registers (00h, 02h, etc.) are currently defined, odd register (01h,

03h, etc.) accesses are reserved for future expansion.

Note that shadowing of the control register file on the AC‘97 Controller is an option left open to the

implementation of the AC‘97 Controller. The AC‘97 CODEC’s control register file is nonetheless

required to be readable as well as writeable to provide more robust testability.

Bit Description

15 Frame Valid

14 Slot 1 Primary CODEC Valid Command Address bit (Primary CODEC only)

13 Slot 2 Primary CODEC Valid Command Data bit (Primary CODEC only)

Slot 3-12 Valid Data bits

12 Slot 3: PCM Left channel

11 Slot 4: PCM Right channel

10 Slot 5: Modem Line 1 (not used on STAC9752/9753)

9 Slot 6: Alternative PCM1 Left

8 Slot 7: Alternative PCM2 Left

7 Slot 8: Alternative PCM2 Right

6 Slot 9: Alternative PCM1 Right

5 Slot 10: SPDIF Left

4 Slot 11: SPDIF Right

3 Slot 12: Audio GPIO

2 Reserved (Set to 0)

1-0 2-bit CODEC ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary)

Note: The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

35 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

AC-Link output frame slot 1 communicates control register address, and write/read command infor-

mation to the STAC9752/9753.

The first bit (MSB) sampled by AC‘97 indicates whether the current control transaction is a read or a

write operation. The following 7 bit positions communicate the targeted control register address. The

trailing 12 bit positions within the slot are reserved and must be stuffed with 0 by the AC‘97 Control-

ler.

5.3.3. Slot 2: Command Data Port

The command data port is used to deliver 16-bit control register write data in the event that the cur-

rent command port operation is a write cycle (as indicated by Slot 1, bit 19).

• Bit(19:4) Control Register Write Data (Stuffed with 0 if current operation is a read)

• Bit(3:0) Reserved (Stuffed with 0)

If the current command port operation is a read then the entire slot time must be stuffed with 0 by the

AC‘97 Controller.

5.3.4. Slot 3: PCM Playback Left Channel

AC-Link output frame slot 3 is the composite digital audio left playback stream. In a typical “Games

Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the

AC‘97 Controller or host processor) with music synthesis output samples. If a sample stream of res-

olution less than 20-bits is transferred, the AC‘97 Controller must stuff all trailing non-valid bit posi-

tions within this time slot with 0.

The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.3.5. Slot 4: PCM Playback Right Channel

AC-Link output frame slot 4 is the composite digital audio right playback stream. In a typical “Games

Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the

AC‘97 Controller or host processor) with music synthesis output samples. If a sample stream of res-

olution less than 20-bits is transferred, the AC‘97 Controller must stuff all trailing non-valid bit posi-

tions within this time slot with 0.

The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.3.6. Slot 5: Modem Line 1 Output Channel

Audio output frame slot 5 is reserved for modem operation and is not used by the STAC9752/9753.

5.3.7. Slot 6 - 11: DAC

The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

Table 8. Command Address Port Bit Assignments

Bit Description Comments

19 Read/Write command 1= read, 0 = write

18:12 Control Register Index Sixty-four 16-bit locations, addressed on even byte boundaries

11:0 Reserved Stuffed with 0

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

36 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

5.3.8. Slot 12: Audio GPIO Control Channel

AC-Link output frame slot 12 contains the audio GPIO control outputs.

5.4. AC-Link Input Frame (SDATA_IN)

The AC-Link input frame data streams correspond to the multiplexed bundles of all digital input data

targeting the AC‘97 Controller. As is the case for audio output frame, each AC-Link input frame con-

sists of 12 20-bit time slots. Slot 0 is a special reserved time slot containing 16-bits which are used

for AC-Link protocol infrastructure.

The following diagram illustrates the time slot-based AC-Link protocol.

Figure 17. STAC9752/9753 Audio Input Frame

A new AC-Link input frame begins with a low to high transition of SYNC. SYNC is synchronous to

the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97

CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of

AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97

CODEC transitions SDATA_IN into the first bit position of slot 0 (“CODEC Ready” bit). Each new bit

position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the

AC‘97 Controller on the falling edge of BIT_CLK. This sequence ensures that data transitions and

subsequent sample points for both incoming and outgoing data streams are time aligned.

Figure 18. Start of an Audio Input Frame

SDATA_IN’s composite stream is MSB first with all non-valid bit positions (for assigned and/or unas-

signed time slots) stuffed with 0 by the AC‘97 CODEC. SDATA_IN data is sampled on the falling

edges of BIT_CLK.

SYNC

BIT_CLK

SDATA_IN

slot1 slot2

End of previous audio frame

slot(12)

"0" 19

Data Phase

20.8 uS (48 kHZ)Tag Phase

12.288 MHz

Time Slot "Valid" Bits Slot 1 Slot 2 Slot 3 Slot 12

("1" = time slot contains valid PCM data)

valid

"0" 19 19"0"

Frame

19"0" "0""0" "0"

SYNC

BIT_CLK

SDATA_IN

slot1 slot2

End of previous audio frame

Codec

Ready

SYNC

detected

first

SDATA_OUT

bit of frame

STAC9753XXTAEB2X

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Buy STAC9753XXTAEB2X

Manufacturer:

Tempo Semiconductor

Description:

Interface - CODECs AC97 2.3 2-CH AUDIO CODEC

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STAC9753XXTAEB2X

STAC9753XXTAEB2X

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