STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
IDT™
57 STAC9752/9753
REV 3.3 1206
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
This register is used to control the 3D stereo enhancement function, IDT Surround 3D (SS3D), built
into the AC'97 component. Note that register bits DP3-DP2 are used to control the separation ratios
in the 3D control for LINE_OUT. SS3D provides for a wider soundstage extending beyond the nor-
mal 2-speaker arrangement. Note that the 3D bit in the general purpose register (20h) must be set to
1 to enable SS3D functionality to allow the bits in 22h to take effect. The three separation ratios are
implemented. The separation ratio defines a series of equations that determine the amount of depth
difference (High, Medium, and Low) perceived during 2-channel playback. The ratios provide for
options to narrow or widen the soundstage.
8.1.17. Audio Interrupt and Paging (24h)
Default: 0000h
Bit(s) Reset Value Name Description
15:4 0 RESERVED Bits not used, should read back 0
3:2 0 DP3, DP2
LINE_OUT SEPARATION RATIO
DP3 DP2 effect
0 0 0 ( OFF )
0 1 3 ( LOW )
1 0 4.5 ( MED )
1 1 6 ( HIGH )
1:0 0 RESERVED Bits not used, should read back 0
D15 D14 D13 D12 D11 D10 D9 D8
I4 I3 I2 I1 I0 RESERVED
D7 D6 D5 D4 D3 D2 D1 D0
RESERVED PG3 PG2 PG1 PG0
Bit(s) Reset Value Access Name Description
15 0 Read / Write I4
0 = Interrupt is clear
1 = Interrupt is set
Interrupt event is cleared by writing a 1 to this bit.
The interrupt bit will change regardless of condition of interrupt
enable (I0) status. An interrupt in the GPI in slot 12 in the ACLink
will follow this bit change when interrupt enable (I0) is unmasked.
14-13 0 Read Only I3-I2
Interrupt Cause
00 = Reserved
01 = Sense Cycle Complete, sense info available.
10 = Change in GPIO input status
11 = Sense Cycle Complete and Change in GPIO input status.
These bits will reflect the general cause of the first interrupt event
generated. It should be read after interrupt status has been
confirmed as interrupting. The information should be used to scan
possible interrupting events in proper pages.
12 0 Read / Write I1
Sense Cycle
0 = Sense Cycle not in Progress
1 = Sense Cycle Start.
Writing a 1 to this bit causes a sense cycle start if supported. If
sense cycle is not supported this bit is read only.
