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STAC9753XXTAEB2X

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84P85-P87P88-P90P91-P93P94-P95
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
IDT™
40 STAC9752/9753
REV 3.3 1206
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
5.5. AC-Link Interoperability Requirements and Recommendations
5.5.1. “Atomic slot” Treatment of Slot 1 Address and Slot 2 Data
Command or Status Address and Data cannot be split across multiple AC-Link frames. The following
transactions require that valid Slot 1 Address and valid Slot 2 Data be treated as “atomic” (insepara-
ble) with Slot 0 Tag bits for Address and Data set accordingly (that is, both valid):
1. AC‘97 Digital Controller write commands to Primary CODECs
2. AC‘97 CODEC status responses
Whenever the AC‘97 Digital Controller addresses a Primary CODEC or an AC‘97 CODEC responds
to a read command, Slot 0 Tag bits should always be set to indicate actual Slot 1 and Slot 2 data
validity.
When the AC‘97 Digital Controller addresses a Secondary CODEC, the Slot 0 Tag bits for Address
and Data must be 0. A non-zero, 2-bit CODEC ID in the LSBs of Slot 0 indicates a valid Read or
Write Address in Slot 1, and the Slot 1 R/W bit indicates presence or absence of valid Data in Slot 2.
Table 11. Primary CODEC Addressing: Slot 0 Tag Bits
Function
Slot 0, bit 15
(Valid
Frame)
Slot 0, bit 14
(Valid Slot 1
Address)
Slot 0, bit 13
(Valid Slot 2 Data)
Slot 0, Bits 1-0
(CODEC ID)
AC‘97 Digital Controller Primary
Read Frame N, SDATA_OUT
1 1 0 00
AC‘97 Digital Controller Primary
Write Frame N, SDATA_OUT
1 1 1 00
AC‘97 CODEC Status Frame
N+1, SDATA_IN
1 1 1 00
Table 12. Secondary CODEC Addressing: Slot 0 Tag Bits
Function
Slot 0, bit 15
(Valid
Frame)
Slot 0, bit 14
(Valid Slot 1
Address)
Slot 0, bit 13
(Valid Slot 2
Data)
Slot 0, Bits
1-0
(CODEC ID)
AC‘97 Digital Controller
Secondary Read Frame N,
SDATA_OUT
1 0 0 01, 10, or 11
AC‘97 Digital Controller
Secondary Write Frame N,
SDATA_OUT
1 0 0 01, 10, or 11
AC‘97 CODEC Status Frame N+1,
SDATA_IN
1 1 1 00
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
IDT™
41 STAC9752/9753
REV 3.3 1206
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
5.6. Slot Assignments for Audio
Figure 19. Bi-directional AC-Link Frame with Slot assignments
Note: The DAC & ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
The AC-Link output slots dedicated to audio are defined as follows:
The AC-Link input slots dedicated to audio are defined as follows:
Note: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
Table 13. AC-Link Slot Definitions
Slot Name Description
3 PCM L DAC playback 20-bit PCM data for Left channel
4 PCM R DAC playback 20-bit PCM data for Right channel
6 PCM Center 20-bit PCM data for Center channel
7 PCM L Surround 20-bit PCM data for L Surround channel
8 PCM R Surround 20-bit PCM data for R Surround channel
9 PCM LFE 20-bit PCM data for LFE channel
10:11 SPDIF Out 20-bit SPDIF Output
12 Reserved Reserved
Table 14. AC-Link Input Slots Dedicated To Audio
Slot Name Description
3 PCM L ADC record 20-bit PCM data from Left input
4 PCM R ADC record 20-bit PCM data from Right inputs
6 Dedicated Microphone ADC 20-bit PCM data from optional 3rd ADC input
7 Vendor reserved Vendor specific (enhanced input for docking, array mic, etc.)
8 Vendor reserved Vendor specific (enhanced input for docking, array mic, etc.)
9 Vendor reserved Vendor specific (enhanced input for docking, array mic, etc.)
12 Audio Interrupt
Provides optional interrupt capability for Audio CODEC (not usable when
a modem is present)
PCM
MIC
Vendor
RSVD
Vendor
RSVD
LINE2
ADC
HSET
ADC
Vendor
RSVD
STATUS
ADDR
OUTGOING STREAMS
(Controller output - SDATA_OUT)
INCOMING STREAMS
(codec output - SDATA_IN)
SYNC
TAG PHASE
DATA PHASE
PCM
LEFT
CMD
ADDR
NA
PCM
LSURR
PCM
LFE
SPDIFTAG
CMD
DATA
PCM
RT
PCM
CTR
PCM
RSURR
SPDIF
IO
CTRL
PCM
LEFT
LINE1
ADC
TAG
STATUS
DATA
PCM
RT
IO
STATUS
SLOTS
0 1 2 3 4 5 6 7 8 9 10 11 12
Slot 12 can be used by the
AC'97 Codec if a Modem
Codec is not present.
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
IDT™
42 STAC9752/9753
REV 3.3 1206
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
Table 15. Audio Interrupt Slot Definitions
Bit Description
19-1 Reserved (Audio CODEC will return zeros in bits 19-1)
0
Optional: Assertion = 1 will cause interrupt to be propagated to Audio controller system interrupt. See
register 24h definition for enabling mechanism.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84P85-P87P88-P90P91-P93P94-P95

STAC9753XXTAEB2X

Mfr. #:
Buy STAC9753XXTAEB2X
Manufacturer:
Tempo Semiconductor
Description:
Interface - CODECs AC97 2.3 2-CH AUDIO CODEC
Lifecycle:
New from this manufacturer.
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