STAC9753XXTAEB2X Datasheet STAC9753XXTAEB2X, STAC9753XXTAEB2XR | P67-P69

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

67 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

8.2.8. GPIO Pin Mask Register (52h)

Default: 0000h

8.2.9. GPIO Pin Status Register (54h)

Default: 0000h

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED

GW1

(GPIO1)

GW0

(GPIO0)

Bit(s) Access Reset Value Name Description

15:2 Read Only 0 RESERVED Bit not used, should read back 0

1 Read / Write 0 GW1

0 = GPIO1 interrupt not passed to GPIO_INT slot 12.

1 = GPIO1 interrupt is passed to GPIO_INT slot 12.

0 Read / Write 0 GW0

0 = GPIO0 interrupt not passed to GPIO_INT slot 12.

1 = GPIO0 interrupt is passed to GPIO_INT slot 12.

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GI1 (GPIO1) GI0 (GPIO0)

Bit(s) Access Reset Value Name Description

15:2 Read Only 0 RESERVED Bits not used, should read back 0

1 Read / Write x GI1

When GPIO1 is configured as output and Register h74 bit[0] = 0

(default), the value of this register will be placed on the GPIO1

pad.

When GPIO1 is configured as output and Register h74 bit[0] =1,

the GPIO1 pad will get its value from slot12.

When GPIO1 is configured as input and configured as a sticky bit,

writing a 1 does nothing, writing a 0 clears this bit.

When GPIO1 is configured as input, this register reflects the value

on the GPIO1 pad after interpretation of the polarity and sticky

configurations.

0 Read / Write x GI0

When GPIO0 is configured as output and Register h74 bit[0] = 0

(default), the value of this register will be placed on the GPIO0

pad.

When GPIO0 is configured as output and Register h74 bit[0] =1,

the GPIO0 pad will get its value from slot12.

When GPIO0 is configured as input and configured as a sticky bit,

writing a 1 does nothing, writing a 0 clears this bit.

When GPIO0 is configured as input, this register reflects the value

on the GPIO0 pad after interpretation of the polarity and sticky

configurations.

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

68 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

8.3. Extended CODEC Registers Page Structure Definition

Registers 60h-68h are the Extended CODEC Registers: These registers allow for the defi-

nition of further capabilities. These bits provide a paged address space for extended

CODEC information. The Page Selector bits in the Audio Interrupt and Paging register

(Register 24h bits 3:0) control the page of information viewed through this page window.

8.3.1. Extended Registers Page 00

Page 00 of the Extended CODEC Registers is reserved for vendor specific use. Driver writ-

ers should not access these registers unless the Vendor ID register has been checked first

to ensure that the vendor of the AC'97 component has been identified and the usage of the

vendor defined registers understood.

8.3.2. Extended Registers Page 01

The usage of Page 01 of the Extended CODEC Registers is defined in Register 24h found

in Section 8.1.17: page57.

8.3.3. Extended Registers Page 02, 03

Pages 02 and 03 of the Extended CODEC Registers are reserved for future use.

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

69 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

8.4. STAC9752/9753 Paging Registers

The AC’97 Specification Rev 2.3 uses a paging mechanism in order to increase the number of regis-

ters. The registers currently used in the paging are 60h to 6Eh. For additional information about the

Extended CODEC Registers, please refer to Section 8.3: page68.

One of two pages can be made active at any time, set in Register 24h. Register 24h is the Audio

Interrupt and Paging Register. Additional details about Register 24h is located in Section 8.1.17:

page57.

If page 00h is active, registers 60h to 6Eh are Vendor Specific.

If page 01h is active, registers 60h to 6Eh have the following functionality:

8.4.1. CODEC Class/Rev (60h Page 01h)

Default: 12xxh

Reg NAME FUNCTION Location

60h CODEC Class/Revision

Provides the CODEC Class and a Vendor specified revision

identifier.

8.4.1: page69

62h PCI SVID

Allows for population by the system BIOS to identify the PCI

Sub System Vendor ID.

8.4.2: page70

64h PCI SSID

Allows for population by the system BIOS to identify the PCI

Sub System ID.

Note:: page70

66h Function Select

Provides the type of audio function being selected and which

jack conductor the selected value is measured from.

Note:: page70

68h Function Information

Includes information about Gain, Inversion, Buffer delays,

Information Validity, and Function Information presence.

8.4.5: page72

6Ah Sense Register

Includes information about the connector/jack location, Input

verses Output sensing, the order of the sense results, and

the IDT specific sense results.

8.4.7: page74

6Ch Reserved

6Eh Reserved

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED CL4 CL3 CL2 CL1 CL0

D7 D6 D5 D4 D3 D2 D1 D0

RV7 RV6 RV5 RV4 RV3 RV2 RV1 RV0

Bit(s) Reset Value Name Description

15-13 Reserved Reserved-not defined

STAC9753XXTAEB2X

Mfr. #:

Buy STAC9753XXTAEB2X

Manufacturer:

Tempo Semiconductor

Description:

Interface - CODECs AC97 2.3 2-CH AUDIO CODEC

Lifecycle:

New from this manufacturer.

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STAC9753XXTAEB2X

STAC9753XXTAEB2X

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