STAC9753XXTAEB2X Datasheet STAC9753XXTAEB2X, STAC9753XXTAEB2XR | P58-P60

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

58 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

8.1.18. Powerdown Ctrl/Stat (26h)

Default: 000Fh

11 0 Read / Write I0

Interrupt Enable

0 = Interrupt generation is masked.

1 = Interrupt generation is un-masked.

The driver should not un-mask the interrupt unless ensured by the

AC ‘97 controller that no conflict is possible with modem slot 12 -

GPI functionality. Some AC’97 2.2 compliant controllers will not

likely support audio CODEC interrupt infrastructure. In either case,

S/W should poll the interrupt status after initiating a sense cycle

and wait for Sense Cycle Max Delay to determine if an interrupting

event has occurred.

10:4 0 Read Only RESERVED Bits not used, should read back 0

3:0 0 Read / Write PG3:PG0

Page Selector

0h = Vendor Specific

1h = Page ID 01 (See Section 8.4 for additional information on the

Paging Registers)

Fh = Reserved Pages

This register is used to select a descriptor of 16 word pages

between registers 60h to 6Fh. Value 0h is used to select vendor

specific space to maintain compatibility with AC’97 2.2 vendor

specific registers.

System S/W determines implemented pages by writing the page

number and reading the value back. All implemented pages must

be consecutive. (i.e., page 2h cannot be implemented without page

1h).

These registers are NOT reset on RESET#.

D15 D14 D13 D12 D11 D10 D9 D8

EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED REF ANL DAC ADC

Bit(s) Reset Value Name Description

15 0 EAPD

1 = Forces EAPD pad to Vdd

0 = Forces EAPD pad to GND

14 0 PR6

0 = Headphone Amp powered up

1 = Headphone Amp powered down

13 0 PR5

0 = Digital Clk active

1 = Digital Clk disable.

12 0 PR4

0 = digital active

1 = Powerdown: PLL, AC-Link, Xtal oscillator;

11 0 PR3

0 = VREF and VREFOUT are active

1 = VREF and VREFOUT are powered down, and PR2 is asserted in

analog block

10 0 PR2

0 = analog active

1 = all signal path analog is powered down

9 0 PR1

0 = DAC powered up

1 = DAC powered down

Bit(s) Reset Value Access Name Description

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

59 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

8.1.18.1. Ready Status

The lower half of this register is read only status, a 1 indicating that each subsection is “ready”.

Ready is defined as the subsection's ability to perform in its nominal state. When this register is writ-

ten, the bit values that come in on AC-Link will have no effect on read-only bits 0-7.

When the AC-Link “CODEC Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the

AC-Link and AC'97 control and status registers are in a fully operational state. The AC'97 controller

must further probe this Powerdown Control/Status Register to determine exactly which subsections,

if any, are ready. When this register is written, the bit values that come in on AC-Link will have no

effect on read-only bits 0-7.

8.1.18.2. Powerdown Controls

The STAC9752/9753 is capable of operating at reduced power when no activity is required. The

state of power down is controlled by the Powerdown Register (26h). See the section “Low Power

Modes” for more information.

8.1.18.3. External Amplifier Power Down Control Output

The EAPD bit 15 of the Powerdown Control/Status Register (Index 26h) directly controls the output

of the EAPD output, pin 45, and produces a logical 1 when this bit is set to logic high. This function is

used to control an external audio amplifier power down. EAPD = 0 places approximately 0V on the

output pin, enabling an external audio amplifier. EAPD = 1 places approximately DVdd on the output

pin, disabling the external audio amplifier. Audio amplifiers that operate with reverse polarity will

likely require an external inverter to maintain software driver compatibility.

EAPD can also act as a GPIO. See Section 8.4.11: page77. The GPIO controls in Section8.2:

page64 have no effect on EAPD.

8.1.19. Extended Audio ID (28h)

Default: 0A05h

8 0 PR0

0 = ADC powered up

1 = ADC powered down

7:4 0 RESERVED Bit not used, should read back 0

3 1 REF

Read Only --- VREF status

1 = VREFs enabled

2 1 ANL

Read Only ---- ANALOG MIXERS, etc. Status

1 = Analog Mixers ready.

1 1 DAC

Read Only ---- DAC Status

1 = DAC ready to playback

0 1 ADC

Read Only ---- ADC Status

1 = ADC ready to record

D15 D14 D13 D12 D11 D10 D9 D8

ID1 ID0 RESERVED AMAP RSVD

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED DSA1 DSA0 RSVD SPDIF RSVD VRA

Bit(s) Reset Value Name Description

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

60 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

The Extended Audio ID register is a read only register except for bits D4 and D5. ID1 and ID0 echo

the configuration of the CODEC as defined by the programming of pins 45 and 46 externally. The

primary CODEC returns “00”, while any other code identifies the CODEC as one of three secondary

CODEC possibilities. The AMAP bit, D9, will return a 1 indicating that the CODEC supports the

optional “AC’97 2.3 compliant AC-Link slot to audio DAC mappings”.The default condition assumes

that 0 is loaded into the DSA0 and DSA1 bits of the Extended Audio ID (Index 28h). With 0 in the

DSA1 and DSA0 bits, the CODEC slot assignments are as per the AC’97 specification recommen-

dations. If the DSA1 and DSA0 bits do not contain 0, the slot assignments are as per the table in the

section describing the Extended Audio ID (Index 28h). The VRA bit, D0, will return a 1 indicating that

the CODEC supports the optional variable sample rate conversion as defined by the AC’97 specifi-

cation.

Table 18. Extended Audio ID Register Functions

Bit Name Access Reset Value Function

15:14 ID [1,0] Read only

variable 0,0 = XTAL_OUT grounded (Note 1)

CID1#, CID0# = XTAL_OUT crystal or floating

13:12 RESERVED Read only 00 Bits not used, should read back 00

11:10 REV[1:0] Read only 10 Indicates CODEC is AC’97 Rev 2.3 compliant

9:6 RSVD Read only 0 Reserved

5:4 DSA [1,0] Read/Write

00 DAC slot assignment

If CID[1:0] = 00 then DSA[1:0] resets to 00

If CID[1:0] = 01 then DSA[1:0] resets to 01

If CID[1:0] = 10 then DSA[1:0] resets to 01

If CID[1:0] = 11 then DSA[1:0] resets to 10

00 = left slot 3, right slot 4

01 = left slot 7, right slot 8

10 = left slot 6, right slot 9

11 = left slot 10, right slot 11

3 RSVD Read only 0 RESERVED

2 SPDIF Read only 1

0 = SPDIF pulled high on reset, SPDIF disabled

1 = default, SPDIF enabled (Note 2)

1 RSVD Read only 0 RESERVED

0 VRA Read only 1 Variable sample rates supported (Always = 1)

1. External CID pin status (from analog) these bits are the logical inversion of the pin polarity (pin 45-46).

These bits are zero if XTAL_OUT is grounded with an alternate external clock source in primary mode

only. Secondary mode can either be through BIT CLK driven or 24MHz clock driver, with XTAL_OUT

floating.

2. If pin 48 is held high at powerup, this bit will be held to zero, to indicate the SPDIF is not available.

Pin 48: To Enable SPDIF, use an external 1KΩ -10KΩ pulldown resistor. To Disable SPDIF, use an

external 1KΩ -10KΩ pullup resistor. Do NOT leave Pin 48 floating.

STAC9753XXTAEB2X

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Buy STAC9753XXTAEB2X

Manufacturer:

Tempo Semiconductor

Description:

Interface - CODECs AC97 2.3 2-CH AUDIO CODEC

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STAC9753XXTAEB2X

STAC9753XXTAEB2X

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