STAC9753XXTAEB2X Datasheet STAC9753XXTAEB2X, STAC9753XXTAEB2XR | P4-P6

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

4 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

8.2.6. GPIO Pin Polarity/Type Register (4Eh) .............................................................................66

8.2.7. GPIO Pin Sticky Register (50h) .........................................................................................66

8.2.8. GPIO Pin Mask Register (52h) ..........................................................................................67

8.2.9. GPIO Pin Status Register (54h) ........................................................................................67

8.3. Extended CODEC Registers Page Structure Definition ..................................................................68

8.3.1. Extended Registers Page 00 .............................................................................................68

8.3.2. Extended Registers Page 01 .............................................................................................68

8.3.3. Extended Registers Page 02, 03 .......................................................................................68

8.4. STAC9752/9753 Paging Registers .................................................................................................69

8.4.1. CODEC Class/Rev (60h Page 01h) ...............................................................................69

8.4.2. PCI SVID (62h Page 01h) ............................................................................................... 70

8.4.3. PCI SSID (64h Page 01h) ............................................................................................... 70

8.4.4. Function Select (66h Page 01h) ......................................................................................71

8.4.5. Function Information (68h Page 01h) ..............................................................................72

8.4.6. Digital Audio Control (6Ah, Page 00h) ...............................................................................73

8.4.7. Sense Details (6Ah Page 01h) ........................................................................................74

8.4.8. Revision Code (6Ch) ........................................................................................................76

8.4.9. Analog Special (6Eh) .........................................................................................................76

8.4.10. Analog Current Adjust (72h) ............................................................................................ 77

8.4.11. EAPD Access Register (74h) ..........................................................................................77

8.4.12. High Pass Filter Bypass (78h) ........................................................................................78

8.5. Vendor ID1 and ID2 (Index 7Ch and 7Eh) ......................................................................................79

8.5.1. Vendor ID1 (7Ch) .............................................................................................................79

8.5.2. Vendor ID2 (7Eh) ...............................................................................................................79

9. LOW POWER MODES ...........................................................................................................80

10. MULTIPLE CODEC SUPPORT ............................................................................................82

10.1. Primary/Secondary CODEC Selection ..........................................................................................82

10.1.1. Primary CODEC Operation ............................................................................................ 82

10.1.2. Secondary CODEC Operation ........................................................................................82

10.2. Secondary CODEC Register Access Definitions ..........................................................................83

11. TESTABILITY ........................................................................................................................84

11.0.1. ATE Test Mode ................................................................................................................84

12. PIN DESCRIPTION ................................................................................................................85

12.1. Digital I/O ......................................................................................................................................86

12.2. Analog I/O ....................................................................................................................................87

12.3. Filter/References ..........................................................................................................................88

12.4. Power and Ground Signals ..........................................................................................................88

13. ORDERING INFORMATION ..................................................................................................89

14. PACKAGE DRAWING ...........................................................................................................89

15. 48-PIN LQFP SOLDER REFLOW PROFILE .........................................................................90

15.1. Standard Reflow Profile Data ........................................................................................................90

15.2. Pb Free Process - Package Classification Reflow Temperatures .................................................91

16. APPENDIX A: PROGRAMMING REGISTERS .....................................................................92

17. REVISION HISTORY .............................................................................................................94

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

5 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

LIST OF FIGURES

Figure 1. Block Diagram .................................................................................................................................8

Figure 2. Cold Reset Timing .........................................................................................................................16

Figure 3. Warm Reset Timing .......................................................................................................................16

Figure 4. Clocks Timing ...............................................................................................................................17

Figure 5. Data Setup and Hold Timing .........................................................................................................18

Figure 6. Signal Rise and Fall Times Timing ................................................................................................18

Figure 7. AC-Link Low Power Mode Timing ..............................................................................................19

Figure 8. ATE Test Mode Timing ...............................................................................................................19

Figure 9. Typical Connection Diagram ..........................................................................................................20

Figure 10. Split Independent Power Supply Operation .................................................................................22

Figure 11. AC-Link to its Companion Controller ...........................................................................................23

Figure 12. CODEC Clock Source Detection .................................................................................................. 24

Figure 13. STAC9752/9753 Powerdown Timing ..........................................................................................27

Figure 14. Bi-directional AC-Link Frame with Slot assignments ...................................................................29

Figure 15. AC-Link Audio Output Frame ......................................................................................................33

Figure 16. Start of an Audio Output Frame ...................................................................................................33

Figure 17. STAC9752/9753 Audio Input Frame ...........................................................................................36

Figure 18. Start of an Audio Input Frame ......................................................................................................36

Figure 19. Bi-directional AC-Link Frame with Slot assignments ...................................................................41

Figure 20. STAC9752 2-Channel Mixer Functional Diagram ........................................................................44

Figure 21. STAC9753 2-Channel Mixer Functional Diagram .......................................................................44

Figure 22. Example of STAC9752/9753 Powerdown/Powerup flow ...........................................................80

Figure 23. Powerdown/Powerup flow with analog still alive .........................................................................81

Figure 24. Pin Description Drawing ...............................................................................................................85

Figure 25. Reflow Profile ..............................................................................................................................90

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

6 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

LIST OF TABLES

Table 1. Clock Mode Configuration ...............................................................................................................17

Table 2. Common Clocks and Sources .........................................................................................................18

Table 3. Recommended CODEC ID strapping .............................................................................................26

Table 4. AC-Link output slots (transmitted from the Controller) .....................................................................29

Table 5. The AC-Link input slots (transmitted from the CODEC) ..................................................................30

Table 6. VRA Behavior ..................................................................................................................................31

Table 7. Output Slot 0 Bit Definitions ............................................................................................................34

Table 8. Command Address Port Bit Assignments ........................................................................................35

Table 9. Status Address Port Bit Assignments ..............................................................................................37

Table 10. Status Data Port Bit Assignments .................................................................................................. 38

Table 11. Primary CODEC Addressing: Slot 0 Tag Bits ................................................................................40

Table 12. Secondary CODEC Addressing: Slot 0 Tag Bits ...........................................................................40

Table 13. AC-Link Slot Definitions .................................................................................................................41

Table 14. AC-Link Input Slots Dedicated To Audio .......................................................................................41

Table 15. Audio Interrupt Slot Definitions ......................................................................................................42

Table 16. Digital PC Beep Examples .............................................................................................................46

Table 17. Programming Registers .................................................................................................................47

Table 18. Extended Audio ID Register Functions ..........................................................................................60

Table 19. AMAP compliant ............................................................................................................................63

Table 20. Hardware Supported Sample Rates ..............................................................................................63

Table 21. Supported Jack and Microphone Sense Functions .......................................................................71

Table 22. Reg 68h Default Values .................................................................................................................73

Table 23. Gain or Attenuation Examples .......................................................................................................73

Table 24. Register 68h/Page 01h Bit Overview .............................................................................................73

Table 25. Sensed Bits (Outputs) ...................................................................................................................75

Table 26. Sensed Bits (Inputs) ......................................................................................................................75

Table 27. Low Power Modes .........................................................................................................................80

Table 28. CODEC ID Selection .....................................................................................................................82

Table 29. Secondary CODEC Register Access Slot 0 Bit Definitions ...........................................................83

Table 30. Test Mode Activation .....................................................................................................................84

Table 31. ATE Test Mode Operation .............................................................................................................84

Table 32. Digital Connection Signals .............................................................................................................86

Table 33. Analog Connection Signals ...........................................................................................................87

Table 34. Filtering and Voltage References .................................................................................................. 88

Table 35. Power and Ground Signals ............................................................................................................88

STAC9753XXTAEB2X

Mfr. #:

Buy STAC9753XXTAEB2X

Manufacturer:

Tempo Semiconductor

Description:

Interface - CODECs AC97 2.3 2-CH AUDIO CODEC

Lifecycle:

New from this manufacturer.

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STAC9753XXTAEB2X

STAC9753XXTAEB2X

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