STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
IDT™
65 STAC9752/9753
REV 3.3 1206
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
8.2.2. GPIO Pin Definitions
GPIO pins are programmable to have input/output functionality. The data values (status) for these
pins are all in one register with input/output configuration in a separate register. Control of GPIO pins
configured for output is achieved by setting the corresponding bit in output slot 12; status of GPIO
pins configured for input is returned on input slot 12. The CODEC must constantly set the GPIO pins
that are configured for output, based upon the value of the corresponding bit position of the control
slot 12. The CODEC should ignore output slot 12 bits that correspond to GPIO control pins config-
ured as inputs. The CODEC must constantly update status on input slot 12, based upon the logic
level detected at each GPIO pin configured for input. A GPIO output pin value that is written via
slot 12 in the current frame will not affect the GPIO status that is returned in that particular write
frame.
This slot-12 based control/status protocol minimizes the latency and complexity, especially for
host-based Controllers and host data pump software, and provides high speed monitoring and con-
trol, above what could be achieved with command/status slots. For host-based implementations,
most AC‘97 registers can be shadowed by the driver in order to provide immediate response when
read by the processor, and GPIO pins configured as inputs should be capable of triggering an inter-
rupt upon a change of status.
The AC-Link request for GPIO pin status is always delayed by at least one frame time. Read-Mod-
ify-Write operations across the AC-Link will incur latency that must be accounted for by the software
driver or AC‘97 Digital Controller firmware. PCI retries should be kept to a minimum wherever possi-
ble.
8.2.3. GPIO Pin Implementation
The GPIOs are set to a high impedance state on power-on or a cold reset. It is up to the AC‘97 Digi-
tal Controller to first enable the output after setting it to the desired state.
8.2.4. Extended Modem Status and Control Register (3Eh)
Default: 0100h
D15 D14 D13 D12 D11 D10 D9 D8
RESERVED PRA
D7 D6 D5 D4 D3 D2 D1 D0
RESERVED GPIO
Bit(s) Access Reset Value Name Description
15:9 Read Only 0 RESERVED Bit not used, should read back 0
8 Read / Write 1 PRA
0 = GPIO powered up / enabled
1 = GPIO powered down / disabled
7:1 Read Only 0 RESERVED Bit not used, should read back 0
0 Read Only 0 GPIO
0 = GPIO not ready (powered down)
1 = GPIO ready (powered up)
