STAC9753XXTAEB2X Datasheet STAC9753XXTAEB2X, STAC9753XXTAEB2XR | P82-P84

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

82 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

10. MULTIPLE CODEC SUPPORT

The STAC9752/9753 provides support for the multi-CODEC option according to the Intel AC'97, rev

2.3 specification. By definition, there can be only one Primary CODEC (CODEC ID 00) and up to

three Secondary CODECs (CODEC IDs 01,10, and 11). The CODEC ID functions as a chip select.

Secondary devices therefore have completely orthogonal register sets; each is individually accessi-

ble and they do not share registers.

10.1. Primary/Secondary CODEC Selection

In a multi-CODEC environment the CODEC ID is provided by external programming of pins 45 and

46 (CID0 and CID1). The CID pin electrical function is logically inverted from the CODEC ID desig-

nation. The corresponding pin state and its associated CODEC ID are listed in the “CODEC ID

Selection” table.

10.1.1. Primary CODEC Operation

As a Primary device, the STAC9752/9753 is completely compatible with existing AC'97 definitions

and extensions. Primary CODEC registers are accessed exactly as defined in the AC'97 Component

Specification and AC'97 Extensions. The STAC9752/9753 operates as Primary by default, and the

external ID pins (45 and 46), have internal pull-ups so that these pins may be left as no-connects for

operation as a primary.

When used as the Primary CODEC, the STAC9752/9753 generates the master AC-Link BIT_CLK

for both the AC'97 Digital Controller and any Secondary CODECs. The STAC9752/9753 can support

up to four loads of 10 KΩ and 50 pF on the BIT_CLK output. This is to ensure that up to four CODEC

implementations will not load down the clock output.

10.1.2. Secondary CODEC Operation

When the STAC9752/9753 is configured as a Secondary device the BIT_CLK pin is configured as an

input at power up. Using the BIT_CLK provided by the Primary CODEC insures that everything on

the AC-Link will be synchronous. As a Secondary device it can be defined as CODEC ID 01, 10, or

11 in the two-bit field(s) of the Extended Audio and/or Extended Modem ID Register(s).

Table 28. CODEC ID Selection

CID1 State CID0 State CODEC ID CODEC Status

Dvdd or floating Dvdd or floating 00 Primary

Dvdd or floating 0 V 01 Secondary

0 V Dvdd or floating 10 Secondary

0 V 0 V 11 Secondary

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

83 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

10.2. Secondary CODEC Register Access Definitions

The AC'97 Digital Controller can independently access Primary and Secondary CODEC registers by

using a 2-bit CODEC ID field (chip select) which is defined as the LSBs of Output Slot 0. For Sec-

ondary CODEC access, the AC'97 Digital Controller must invalidate the tag bits for Slot 1 and 2

Command Address and Data (Slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into

the CODEC ID field (Slot 0, bits 1 and 0).

As a Secondary CODEC, the STAC9752/9753 will disregard the Command Address and Command

Data (Slot 0, bits 14 and 13) tag bits when it sees a 2-bit CODEC ID value (Slot 0, bits 1 and 0) that

matches its configuration. In a sense the Secondary CODEC ID field functions as an alternative

Valid Command Address (for Secondary reads and writes) and Command Data (for Secondary

writes) tag indicator.

Secondary CODECs must monitor the Frame Valid bit, and ignore the frame (regardless of the state

of the Secondary CODEC ID bits) if it is not valid. AC'97 Digital Controllers should set the frame valid

bit for a frame with a secondary register access, even if no other bits in the output tag slot except the

Secondary CODEC ID bits are set.

This method is designed to be backward compatible with existing AC'97 controllers and CODECs.

There is no change to output Slot 1 or 2 definitions.

Using three CODECs typically requires a controller to support SDATA_IN2.

Table 29. Secondary CODEC Register Access Slot 0 Bit Definitions

Output Tag Slot (16-bits)

Bit Description

15 Frame Valid

14 Slot 1 Valid Command Address bit (†Primary CODEC only)

13 Slot 2 Valid Command Data bit (†Primary CODEC only)

12-3 Slot 3-12 Valid bits as defined by AC'97

2 Reserved (Set to 0)

†1-0

2-bit CODEC ID field

(00 reserved for Primary; 01, 10, 11 indicate Secondary)

Note: † New definitions for Secondary CODEC Register Access

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

84 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

11. TESTABILITY

The STAC9752/9753 has two test modes. One is for ATE in-circuit test and the other is restricted for

manufacturer’s internal use. The STAC9752/9753 enters the ATE in-circuit test mode if

SDATA_OUT is sampled high at the trailing edge of RESET#. Once in the ATE test mode, the digital

AC-Link outputs (BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE

in-circuit testing of the AC'97 controller. Use of the ATE test mode is the recommended means of

removing the CODEC from the AC-Link when another CODEC is to be used as the primary. This

case will never occur during standard operating conditions. Once either of the two test modes have

been entered, the STAC9752/9753 must be issued another RESET# with all AC-Link signals held

low to return to the normal operating mode.

11.0.1. ATE Test Mode

ATE test mode allows for in-circuit testing to be completed at the board level. For this to work, the

outputs of the device must be driven to a high impedance state (Z). Internal pullups for digital I/O

pins must be disabled in this mode. This mode initiates on the rising edge of RESET# pin. Only a

cold reset will exit the ATE Test Mode.

Note: Pins 31, 33, and 34 are NO CONNECTS.

Table 30. Test Mode Activation

SYNC SDATA_OUT Description

0 0 Normal AC'97 operation

0 1 ATE Test Mode

1 0 IDT Internal Test Mode

1 1 Reserved

Table 31. ATE Test Mode Operation

Pin Name Pin # Function Description

SDATA_OUT 5 1 Must be held high at the rising edge of RESET#

BIT_CLK 6 Z

SDATA_IN 8 Z

SYNC 10 0 Must be held low at rising edge of RESET#

RESET# 11 1

N.C. 31 Z Always an input

N.C. 33 Z Always an input

N.C. 34 Z Always an input

GPIO0 43 Z

GPIO1 44 Z

CID0 45 Z

CID1 46 Z

EAPD 47 Z

SPDIF 48 Z

STAC9753XXTAEB2X

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Buy STAC9753XXTAEB2X

Manufacturer:

Tempo Semiconductor

Description:

Interface - CODECs AC97 2.3 2-CH AUDIO CODEC

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