STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
IDT™
25 STAC9752/9753
REV 3.3 1206
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
ates SYNC by dividing BIT_CLK by 256 and applying some conditioning to tailor its duty cycle. This
yields a 48 KHz SYNC signal whose period defines an audio frame. Data is transitioned on AC-Link
on every rising edge of BIT_CLK, and subsequently sampled by the receiving device on the receiv-
ing side of AC-Link on each immediately following falling edge of BIT_CLK.
4.3. Controller to Multiple CODECs
Several vendor specific methods of supporting multiple CODEC configurations on AC-Link have
been implemented or proposed, including CODECs with selective AC-Link pass-through and con-
trollers with duplicate AC-Links.
Potential implementations include:
• 6-channel audio using 3 x 2-channel CODECs
• Separate CODECs for independent audio and modem AFE
• Docking stations, where one CODEC is in the laptop and another is in the dock
This specification defines support for up to four CODECs on the AC-Link. By definition there can be
one Primary CODEC (ID 00) and up to three Secondary CODECs (IDs 01,10, and 11). The CODEC
ID functions as a chip select. Secondary devices therefore have completely orthogonal register sets;
each is individually accessible and they do not share registers.
Multiple CODEC AC-Link implementations must run off a common BIT_CLK. They can potentially
save Controller pins by sharing SYNC, SDATA_OUT, and RESET# from the AC‘97 Digital Control-
ler. Each device requires its own SDATA_IN pin back to the Controller. This prevents contention of
multiple devices on one serial input line.
Support for multiple CODEC operation necessitates a specially designed Controller. An AC‘97 Digi-
tal Controller that supports multiple CODEC configurations implements multiple SDATA_IN inputs,
supporting one Primary CODEC and up to three Secondary CODECs.
4.3.1. Primary CODEC Addressing
Primary AC‘97 CODECs respond to register read and write commands directed to CODEC ID 00
(see Section 10 for details of the Primary and Secondary CODEC addressing protocols). Primary
devices must be configurable (by hardwiring, strap pin(s), or other methods) as CODEC ID 00, and
reflect this in the two-bit CODEC ID field(s) of the Extended Audio and/or Extended Modem ID Reg-
ister(s).
The Primary CODEC may either drive the BIT_CLK signal or consume a BIT_CLK signal provided
by the digital controller or other clock generator.
4.3.2. Secondary CODEC Addressing
Secondary AC‘97 CODECs respond to register read and write commands directed to CODEC IDs
01, 10, or 11. Secondary devices must be configurable (via hardwiring, strap pin(s), or other meth-
ods) as CODEC IDs 01, 10, or 11 in the two-bit field(s) of the Extended Audio and/or Extended
Modem ID Register(s).
CODECs configured as Secondary must power up with the BIT_CLK pin configured as an input.
Using the provided BIT_CLK signal is necessary to ensure that everything on the AC-Link is syn-
chronous. BIT_CLK is the clock source (multiplied by 2 so that the internal rate is 24.576 MHz).
