STAC9753XXTAEB2X Datasheet STAC9753XXTAEB2X, STAC9753XXTAEB2XR | P76-P78

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

76 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

8.4.8. Revision Code (6Ch)

To access Register 6Ch, Page 00h must be selected in Register 24h.

Default: 00xxh

8.4.9. Analog Special (6Eh)

To access Register 6Eh, Page 00h must be selected in Register 24h.

Default: 1000h

D15 D14 D13 D12 D11 D10 D9 D8

MINORREV

D7 D6 D5 D4 D3 D2 D1 D0

MAJORREV

Bit(s) Reset Value Name Description

15:8 00h MINORREV

Minor Revision ID. These bits are read only and will be updated based on minor

device changes which will not require software changes.

7:0 xxh MAJORREV

Major Revision ID. These bits are read only and will be updated based on major

device changes.

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED AC97MIX RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RSVD

MUTEFIX

DISABLE

ADCSLT1 ADCSLT0 RSVD

MIC GAIN

VAL

SPLYOVR EN SPLYOVR VAL

Bit(s) Reset Value Name Description

15:13 0 RESERVED Bits not used, should read back 0

12 1 AC97MIX

0 = Mixer record contains a mix of all mono and stereo analog input signals,

not the DAC (ALL ANALOG mode).

1 = Mixer record contains a mix of all mono and stereo analog input signals

plus the DAC signal (AC’97 mode).

This bit only has an effect when either Stereo Mix or Mono Mix is selected as

the record source in Reg 1Ah.

The “ALL” mode is useful in conjunction with the POP BYPASS mode (Reg

20h; D15) to record all analog sources, perform further processing in the

digital domain, including combining with other PCM data, and routing through

the DACs directly to Line Out, Headphone Out, or Mono Out.

A Stereo Mix recording will be affected by the setting of the 3D Effects bit

(Reg 20h; D13)

11:7 0 RESERVED Bits not used, should read back 0

6 0

MUTEFIX

DISABLE

0 = MUTE FIX Enabled

1 = MUTE FIX Disabled

When this bit is zero, and either channel is set to -46.5dB attenuation (1Fh),

then that channel is fully muted. When this bit is one, then operation is per

AC’97 specification.

5:4 0 ADCSLT1:0

Select slots for ADC data on ACLINK

00 = Left slot 3, right slot 4

01 = Left slot 7, right slot 8

10 = Left slot 6, right slot 9

11 = Left slot 10, right slot 11

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

77 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

8.4.10. Analog Current Adjust (72h)

To unlock Register 72h, write 0xABBA to Register 70h.

Default: 0000h

8.4.11. EAPD Access Register (74h)

Default: 0800h

3 0 RESERVED RESERVED

2 0 MIC GAIN VAL

Adds +10dB gain to the selected MIC input. Use in conjunction with

BOOSTEN (Reg. 0Eh;D6)

BOOSTEN MICGAINVAL

0 0 = 0 dB

0 1 = 10 dB

1 0 = 20 dB

1 1 = 30 dB

1 0 SPLYOVR_EN

Supply Override bit allows override of the supply detect.

0 = No override on supply detect

1 = Override supply detect with bit 0

0 0

SPLYOVR_VA

Supply Override Value provides the analog voltage operation values.

0 = Force 3.3 v operation

1 = Force 5 V operation

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

INT APOP RESERVED

Bit(s) Reset Value Name Description

15:8 0 Reserved Reserved

7 0 INT_APOP

0 = Anti Pop Enabled

1 = Anti Pop Disabled

The STAC9752/9753 includes an internal power supply anti-pop circuit that

prevents audible clicks and pops from being heard when the CODEC is powered

on and off. This function is accomplished by delaying the charge/discharge of the

VREF capacitor (Pin 27). A C

VREF

value of 1 µF will cause a turn-on delay of

roughly 3 seconds, which will allow the power supplies to stabilize before the

CODEC outputs are enabled. The delay will be extended to 30 seconds if a

VREF

value of 10 µF is used. The CODEC outputs are also kept stable for the

same amount of time at power-off to allow the system to be gracefully turned off.

The Anti Pop bit allows this delay circuit to be bypassed for rapid production

testing. Any external component anti-pop circuit is unaffected by the internal

circuit.

6:0 0 Reserved Reserved

D15 D14 D13 D12 D11 D10 D9 D8

EAPD RESERVED EAPD_OEN RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED INTDIS GPIOACC GPIOSLT12

Bit(s) Reset Value Name Description

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

78 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

8.4.12. High Pass Filter Bypass (78h)

To unlock Register 78h, write 0xABBA to Register 76h.

Default: 0000h

Bit(s) Reset Value Name Description

15 0 EAPD

EAPD data Enable

EAPD data is output on the EAPD pin when bit D11 = 1

EAPD data is input on the EAPD pin when bit D11 = 0

14:12 0 Reserved Bits not used, should read back 0

11 1 EAPD_OEN

EAPD Pin Enable

0 = EAPD configured as input pin

1 = EAPD configured as output pin

10:3 0 Reserved Bits not used, should read back 0

2 0 INTDIS

Interrupt disable option.

Interrupts cleared by writing a 1 to I4 (Reg24h:D15)

0 = Will clear both SENSE and GPIO interrupts

1 = Will only clear SENSE interrupts. GPIO interrupts will have to be cleared in

Reg54h.

1 0 GPIOACC

GPIO ACCESS

0 = ACLINK access from GPIO Pads

1 = ACLINK access from GPIO Register 54h

0 0 GPIOSLT12

0 = GPIO0/1 access via Reg 54h when GPIO is set as an output, for input, Slot

12 data will be 0h.

1 = GPIO0/1 access via Slot 12 when GPIO is set as an output, for inputs,

Reg54h will not be updated.

This can only be used if a modem CODEC is not present in the system and using

Slot 12.

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED ADC HPF BYP

Bit(s) Reset Value Name Description

15:1 0 RESERVED Bits not used, should read back 0

0 0 ADC HPF BYP

0 = ADC High Pass Filter active, (Normal operation)

1 = ADC High Pass Filter Bypass

STAC9753XXTAEB2X

Mfr. #:

Buy STAC9753XXTAEB2X

Manufacturer:

Tempo Semiconductor

Description:

Interface - CODECs AC97 2.3 2-CH AUDIO CODEC

Lifecycle:

New from this manufacturer.

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STAC9753XXTAEB2X

STAC9753XXTAEB2X

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