P87LPC778FDH,529 Datasheet P87LPC778FDH,529 | P13-P15

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data Rev. 01 — 31 March 2004 13 of 79

9397 750 12378

the A/D to stabilize. Prior to the beginning of an A/D conversion, one analog input pin

must be selected for conversion via the AADR1 and AADR0 bits. These bits cannot

be changed while the A/D is performing a conversion.

An A/D conversion is started by setting the ADCS bit, which remains set while the

conversion is in progress. When the conversion is complete, the ADCS bit is cleared

and the ADCI bit is set. When ADCI is set, it will generate an interrupt if the interrupt

system is enabled, the A/D interrupt is enabled (via the EAD bit in the IE1 register),

and the A/D interrupt is the highest priority pending interrupt.

When a conversion is complete, the result is contained in the register DAC0 and can

be read to get the ADC result. This value will not change until another conversion is

started. Before another A/D conversion may be started, the ADCI bit must be cleared

by software. The A/D channel selection may be changed by the same instruction that

sets ADCS to start a new conversion, but not by the same instruction that clears

ADCI.

The connections of the A/D converter are shown in Figure 5.

The ideal A/D result may be calculated as follows:

(1)

Table 4: ADCON - A/D control register (address C0h) bit allocation

Bit addressable; Reset value: 00H

Bit 7 6 5 4 3 2 1 0

Symbol ENADC - - ADCI ADCS RCCLK AADR1 AADR0

Table 5: ADCON - A/D control register (address C0h) bit description

Bit Symbol Description

7 ENADC When ENADC = 1, the A/D is enabled and conversions may take

place. Must be set 10 microseconds before a conversion is started.

ENADC cannot be cleared while ADCS or ADCI are ‘1’.

6, 5 - Reserved for future use. Should not be set to ‘1’ by user programs.

4 ADCI A/D conversion complete/interrupt ﬂag. This ﬂag is set when an

A/D conversion is completed. This bit will cause a hardware

interrupt if enabled and of sufﬁcient priority. Must be cleared by

software.

3 ADCS A/D start. Setting this bit by software starts the conversion of the

selected A/D input. ADCS remains set while the A/D conversion is

in progress and is cleared automatically upon completion. While

ADCS or ADCI are one, new start commands are ignored. See

Table 6 .

2 RCCLK When RCCLK = 0, the CPU clock is used as the A/D clock. When

RCCLK = 1, the internal RC oscillator is used as the A/D clock.

This bit is writable while ADCS and ADCI are 0.

1, 0 AADR1, 0 Along with AADR0, selects the A/D channel to be converted.

These bits can only be written while ADCS and ADCI are 0. See

Table 7 .

Result V

–()

255

–

--------------------------

round result to the nearest integer()×=

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data Rev. 01 — 31 March 2004 14 of 79

9397 750 12378

8.4 A/D timing

The A/D may be clocked in one of two ways. The default is to use the CPU clock as

the A/D clock source. When used in this manner, the A/D completes a conversion in

31 machine cycles. The A/D may be operated up to the maximum CPU clock rate of

20 MHz, giving a conversion time of 9.3 µs. The formula for calculating A/D

conversion time when the CPU clock runs the A/D is: 186 µs / CPU clock rate

(in MHz). To obtain accurate A/D conversion results, the CPU clock must be at least

1 MHz.

The A/D may also be clocked by the on-chip RC oscillator, even if the RC oscillator is

not used as the CPU clock. This is accomplished by setting the RCCLK bit in

ADCON. This arrangement has several advantages. First, the A/D conversion time is

faster at lower CPU clock rates. Also, the CPU may be run at speeds below 1 MHz

without affecting A/D accuracy. Finally, the Power-down mode may be used to

completely shut down the CPU and its oscillator, along with other peripheral

functions, in order to obtain the best possible A/D accuracy.

When the A/D is operated from the RCCLK while the CPU is running from another

clock source, 3 or 4 machine cycles are used to synchronize A/D operation. The time

can range from a minimum of 3 machine cycles (at the CPU clock rate) + 108 RC

clocks to a maximum of 4 machine cycles (at the CPU clock rate) + 112 RC clocks.

Example A/D conversion times at various CPU clock rates are shown in Table 8. In

the table, maximum times for RCCLK = 1 use an RC clock frequency of 6 MHz.

Minimum times for RCCLK = 1 use an RC clock frequency of. Nominal time assume

an ideal RC clock frequency of 6 MHz and an average of 3.5 machine cycles at the

CPU clock rate.

Table 6: ADCON - ADCI, ADCS A/D status

ADCI, ADCS A/D status

0 0 A/D not busy, a conversion can be started

0 1 A/D busy, the start of a new conversion is blocked.

1 0 An A/D conversion is complete. ADCI must be cleared prior to starting a

new conversion.

1 1 An A/D conversion is complete. ADCI must be cleared prior to starting a

new conversion. This state exists for one machine cycle as an A/D

conversion is completed.

Table 7: ADCON - AADR1, AADR0 A/D input selection

AADR1, AADR0 A/D input selected

0 0 AD0 (P0.3)

0 1 AD1 (P0.4)

1 0 AD2 (P0.5)

1 1 AD3 (P0.6)

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data Rev. 01 — 31 March 2004 15 of 79

9397 750 12378

8.4.1 The A/D in Power-down and Idle modes

While using the CPU clock as the A/D clock source, the Idle mode may be used to

conserve power and/or to minimize system noise during the conversion. CPU

operation will resume and Idle mode terminate automatically when a conversion is

complete if the A/D interrupt is active. In Idle mode, noise from the CPU itself is

eliminated, but noise from the oscillator and any other on-chip peripherals that are

running will remain.

The CPU may be put into Power-down mode when the A/D is clocked by the on-chip

RC oscillator (RCCLK = 1). This mode gives the best possible A/D accuracy by

eliminating most on-chip noise sources.

If the Power-down mode is entered while the A/D is running from the CPU clock

(RCCLK = 0), the A/D will abort operation and will not wake up the CPU. The

contents of DAC0 will be invalid when operation does resume.

When an A/D conversion is started, Power-down or Idle mode must be activated

within two machine cycles in order to have the most accurate A/D result. These two

machine cycles are counted at the CPU clock rate. When using the A/D with either

Power-down or Idle mode, care must be taken to insure that the CPU is not restarted

by another interrupt until the A/D conversion is complete. The possible causes of

wake-up are different in Power-down and Idle modes.

A/D accuracy is also affected by noise generated elsewhere in the application, power

supply noise, and power supply regulation. Since the P87LPC778 power pins are

also used as the A/D reference and supply, the power supply has a very direct affect

Table 8: Example A/D conversion times

CPU clock rate RCCLK = 0 RCCLK = 1

minimum nominal maximum

32 kHz NA 563.4 µs 659 µs 757 µs

1 MHz 186 µs 32.4 µs 39.3 µs 48.9 µs

4 MHz 46.5 µs 18.9 µs 23.6 µs 30.1 µs

11.0592 MHz 16.8 µs16µs 20.2 µs 27.1 µs

12 MHz 15.5 µs 15.9 µs 20.1 µs 26.9 µs

16 MHz 11.6 µs 15.5 µs 19.7 µs 26.4 µs

20 MHz 9.3 µs 15.3 µs 19.4 µs 26.1 µs

Fig 5. A/D converter connections.

002aaa616

AD0 (P0.3)

AD1 (P0.4)

A/D CONVERTER

AD2 (P0.5)

AD3 (P0.6)

ADCON

ADCON DAC0ADCON

DAC0

(A/D result, read DAC0)

REF

+ = V

REF

- = V

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P69 P70-P72 P73-P75 P76-P78 P79-P79

P87LPC778FDH,529

Mfr. #:

Buy P87LPC778FDH,529

Manufacturer:

NXP Semiconductors

Description:

IC MCU 8BIT 8KB OTP 20TSSOP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

P87LPC778FDH,529