P87LPC778FDH,529 Datasheet P87LPC778FDH,529 | P64-P66

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data Rev. 01 — 31 March 2004 64 of 79

9397 750 12378

8.16.1 Watchdog feed sequence

If the Watchdog timer is running, it must be fed before it times out in order to prevent

a chip reset from occurring. The Watchdog feed sequence consists of ﬁrst writing the

value 1Eh, then the value E1h to the WDRST register. An example of a Watchdog

feed sequence is shown below.

WDFeed:

mov WDRST,#1eh ; First part of Watchdog feed sequence.

mov WDRST,#0e1h ; Second part of Watchdog feed sequence.

The two writes to WDRST do not have to occur in consecutive instructions. An

incorrect Watchdog feed sequence does not cause any immediate response from the

Watchdog timer, which will still time out at the originally scheduled time if a correct

feed sequence does not occur prior to that time.

After a chip reset, the user program has a limited time in which to either feed the

Watchdog timer or change the timeout period. When a low CPU clock frequency is

used in the application, the number of instructions that can be executed before the

Watchdog overﬂows may be quite small.

8.16.2 Watchdog reset

If a Watchdog reset occurs, the internal reset is active for approximately one

microsecond. If the CPU clock was still running, code execution will begin

immediately after that. If the processor was in Power-down mode, the Watchdog reset

will start the oscillator and code execution will resume after the oscillator is stable.

Table 55: WDCON - Watchdog timer control register (address A7H) bit allocation

Not bit addressable; Reset value: 30H for a Watchdog reset; 10H for other reset sources if the

Watchdog is enabled via the WDTE conﬁguration bit; 00H for other reset sources if the

Watchdog is disabled via the WDTE conﬁguration bit.

Bit 7 6 5 4 3 2 1 0

Symbol - - WDOVF WDRUN WDCLK WDS2 WDS1 WDS0

Table 56: WDCON - Watchdog timer control register (address A7H) bit description

Bit Symbol Description

7, 6 - Reserved for future use. Should not be set to ‘1’ by user programs.

5 WDOVF Watchdog timer overﬂow ﬂag. Set when a Watchdog reset or timer

overﬂow occurs. Cleared when the Watchdog is fed.

4 WDRUN Watchdog run control. The Watchdog timer is started when

WDRUN = 1 and stopped when WDRUN = 0. This bit is forced to

‘1’ (Watchdog running) if the WDTE conﬁguration bit = 1.

3 WDCLK Watchdog clock select. The Watchdog timer is clocked by CPU

clock / 6 when WDCLK = 1 and by the Watchdog RC oscillator

when WDCLK = 0. This bit is forced to 0 (using the Watchdog RC

oscillator) if the WDTE conﬁguration bit = 1.

2 to 0 WDS[2:0] Watchdog rate select.

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data Rev. 01 — 31 March 2004 65 of 79

9397 750 12378

8.17 Additional features

The AUXR1 register contains several special purpose control bits that relate to

several chip features. AUXR1 is described in Tables 58 and 59.

Table 57: Watchdog rate select clock time

WDS[2:0] Timeout clocks Minimum time Nominal time Maximum time

0 0 0 8,192 10 ms 16 ms 23 ms

0 0 1 16,384 20 ms 32 ms 45 ms

0 1 0 32,768 41 ms 65 ms 90 ms

0 1 1 65,536 82 ms 131 ms 180 ms

1 0 0 131,072 165 ms 262 ms 360 ms

1 0 1 262,144 330 ms 524 ms 719 ms

1 1 0 524,288 660 ms 1.05 sec 1.44 sec

1 1 1 1,048,576 1.3 sec 2.1 sec 2.9 sec

Table 58: AUXR1 - AUXR1 register (address A2H) bit allocation

Not bit addressable; Reset value: 00H

Bit 7 6 5 4 3 2 1 0

Symbol KBF BOD BOI LPEP SRST 0 - DPS

Table 59: AUXR1 - AUXR1 register (address A2H) bit description

Bit Symbol Description

7 KBF Keyboard Interrupt Flag. Set when any pin of port 0 that is enabled

for the Keyboard Interrupt function goes LOW. Must be cleared by

software.

6 BOD Brown Out Disable. When set, turns off brownout detection and

saves power. See Section 8.11 “Power monitoring functions” on

page 42 for details.

5 BOI Brown Out Interrupt. When set, prevents brownout detection from

causing a chip reset and allows the brownout detect function to be

used as an interrupt. See Section 8.11 “Power monitoring

functions” on page 42 for details.

4 LPEP Low Power EPROM control bit. Allows power savings in low

voltage systems. Set by software. Can only be cleared by

Power-on or brownout reset. See Section 8.12 “Power reduction

modes” on page 43 for details.

3 SRST Software Reset. When set by software, resets the P87LPC778 as

if a hardware reset occurred.

2 0 This bit contains a hard-wired 0. Allows toggling of the DPS bit by

incrementing AUXR1, without interfering with other bits in the

1 - Reserved for future use. Should not be set to ‘1’ by user programs.

0 DPS Data Pointer Select. Chooses one of two Data Pointers for use by

the program. See text for details.

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data Rev. 01 — 31 March 2004 66 of 79

9397 750 12378

8.17.1 Software reset

The SRST bit in AUXR1 allows software the opportunity to reset the processor

completely, as if an external reset or Watchdog reset had occurred. If a value is

written to AUXR1 that contains a ‘1’ at bit position 3, all SFRs will be initialized and

execution will resume at program address 0000. Care should be taken when writing

to AUXR1 to avoid accidental software resets.

8.17.2 Dual data pointers

The dual Data Pointer (DPTR) adds to the ways in which the processor can specify

the address used with certain instructions. The DPS bit in the AUXR1 register selects

one of the two Data Pointers. The DPTR that is not currently selected is not

accessible to software unless the DPS bit is toggled.

Speciﬁc instructions affected by the Data Pointer selection are:

• INC DPTR: Increments the Data Pointer by 1.

• JMP @A+DPTR: Jump indirect relative to DPTR value.

• MOV DPTR, #data16: Load the Data Pointer with a 16-bit constant.

• MOVCA, @A+DPTR: Move code byte relative to DPTR to the accumulator.

• MOVXA, @DPTR: Move data byte the accumulator to data memory relative to

DPTR.

• MOVX @DPTR, A: Move data byte from data memory relative to DPTR to the

accumulator.

Also, any instruction that reads or manipulates the DPH and DPL registers (the upper

and lower bytes of the current DPTR) will be affected by the setting of DPS. The

MOVX instructions have limited application for the P87LPC778 since the part does

not have an external data bus. However, they may be used to access EPROM

conﬁguration information (see Section 8.18 “EPROM characteristics”).

Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the DPS bit may be

toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,

without the possibility of inadvertently altering other bits in the register.

8.18 EPROM characteristics

Programming of the EPROM on the P87LPC778 is accomplished with a serial

programming method. Commands, addresses, and data are transmitted to and from

the device on two pins after programming mode is entered. Serial programming

allows easy implementation of in-circuit programming of the P87LPC778 in an

application board.

The P87LPC778 contains three signature bytes that can be read and used by an

EPROM programming system to identify the device. The signature bytes designate

the device as an P87LPC778 manufactured by Philips. The signature bytes may be

read by the user program at addresses FC30h, FC31h and FC60h with the MOVC

instruction, using the DPTR register for addressing.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P69 P70-P72 P73-P75 P76-P78 P79-P79

P87LPC778FDH,529

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IC MCU 8BIT 8KB OTP 20TSSOP

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