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P87LPC778FDH,529

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P79
Philips Semiconductors
P87LPC778
CMOS single-chip 8-bit microcontroller
Product data Rev. 01 — 31 March 2004 43 of 79
9397 750 12378
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
If the Brownout Detect function is not required in an application, it may be disabled,
thus saving power. Brownout Detect is disabled by setting the control bit BOD in the
AUXR1 register (AUXR1.6).
8.11.2 Power-on detection
The Power-on Detect has a function similar to the Brownout Detect, but is designed to
work as power comes up initially, before the power supply voltage reaches a level
where Brownout Detect can work. When this feature is activated, the POF flag in the
PCON register is set to indicate an initial power up condition. The POF flag will
remain set until cleared by software.
8.12 Power reduction modes
The P87LPC778 supports Idle and Power-down modes of power reduction.
8.12.1 Idle mode
The Idle mode leaves peripherals running in order to allow them to activate the
processor when an interrupt is generated. Any enabled interrupt source or Reset may
terminate Idle mode. Idle mode is entered by setting the IDL bit in the PCON register
(see Tables 41 and 42).
8.12.2 Power-down mode
The Power-down mode stops the oscillator in order to absolutely minimize power
consumption. Power-down mode is entered by setting the PD bit in the PCON register
(see Tables 41 and 42).
The processor can be made to exit Power-down mode via Reset or one of the
interrupt sources shown in Table 4 0. This will occur if the interrupt is enabled and its
priority is higher than any interrupt currently in progress.
In Power-down mode, the power supply voltage may be reduced to the RAM
keep-alive voltage V
RAM
. This retains the RAM contents at the point where
Power-down mode was entered. SFR contents are not guaranteed after V
DD
has
been lowered to V
RAM
, therefore it is recommended to wake up the processor via
Reset in this case. V
DD
must be raised to within the operating range before the
Power-down mode is exited. Since the Watchdog timer has a separate oscillator, it
may reset the processor upon overflow if it is running during Power-down.
Note that if the Brownout Detect reset is enabled, the processor will be put into reset
as soon as V
DD
drops below the brownout voltage. If Brownout Detect is configured
as an interrupt and is enabled, it will wake up the processor from Power-down mode
when V
DD
drops below the brownout voltage.
When the processor wakes up from Power-down mode, it will start the oscillator
immediately and begin execution when the oscillator is stable. Oscillator stability is
determined by counting 1024 CPU clocks after start-up when one of the crystal
oscillator configurations is used, or 256 clocks after start-up for the internal RC or
external clock input configurations.
Philips Semiconductors
P87LPC778
CMOS single-chip 8-bit microcontroller
Product data Rev. 01 — 31 March 2004 44 of 79
9397 750 12378
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down. These include the Brownout
Detect, Watchdog Timer, and Comparators.
8.12.3 Low voltage EPROM operation
The EPROM array contains some analog circuits that are not required when V
DD
is
less than 4 V, but are required for a V
DD
greater than 4 V. The LPEP bit (AUXR.4),
when set by software, will Power-down these analog circuits resulting in a reduced
supply current. LPEP is cleared only by Power-on reset, so it may be set ONLY for
applications that always operate with V
DD
less than 4 V.
Table 40: Interrupt sources
Wake-up Source Conditions
External Interrupt 0 or 1 The corresponding interrupt must be enabled.
Keyboard Interrupt The keyboard interrupt feature must be enabled and properly
set up. The corresponding interrupt must be enabled.
Comparator 1 or 2 The comparator(s) must be enabled and properly set up. The
corresponding interrupt must be enabled.
Watchdog Timer Reset The Watchdog timer must be enabled via the WDTE bit in the
UCFG1 EPROM configuration byte.
Watchdog Timer Interrupt The WDTE bit in the UCFG1 EPROM configuration byte must
not be set. The corresponding interrupt must be enabled.
Brownout Detect Reset The BOD bit in AUXR1 must not be set (brownout detect not
disabled). The BOI bit in AUXR1 must not be set (brownout
interrupt disabled).
Brownout Detect Interrupt The BOD bit in AUXR1 must not be set (brownout detect not
disabled). The BOI bit in AUXR1 must be set (brownout interrupt
enabled). The corresponding interrupt must be enabled.
Reset Input The external reset input must be enabled.
A/D Converter Must use internal RC clock (RCCLK = 1) for A/D converter to
work in Power-down mode. The A/D must be enabled and
properly set up. The corresponding interrupt must be enabled.
Table 41: PCON - Power control register (address 87H) bit allocation
Not bit addressable; Reset value: 30H for a Power-on reset; 20H for a Brownout reset; 00H for
other reset sources.
Bit 7 6 5 4 3 2 1 0
Symbol SMOD1 SMOD0 BOF POF GF1 GF0 PD IDL
Table 42: PCON - Power control register (address 87H) bit description
Bit Symbol Description
7 SMOD1 When set, this bit doubles the UART baud rate for modes 1, 2, and
3.
6 SMOD0 This bit selects the function of bit 7 of the SCON SFR. When 0,
SCON.7 is the SM0 bit. When 1, SCON.7 is the FE (Framing Error)
flag. See Tables 48 and 49 for additional information.
5 BOF Brown Out Flag. Set automatically when a brownout reset or
interrupt has occurred. Also set at Power-on. Cleared by software.
Refer to Section 8.11 “Power monitoring functions” on page 42 for
additional information.
Philips Semiconductors
P87LPC778
CMOS single-chip 8-bit microcontroller
Product data Rev. 01 — 31 March 2004 45 of 79
9397 750 12378
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.13 Reset
The P87LPC778 has an active LOW reset input when configured for an external
reset. A fully internal reset may also be configured which provides a reset when
power is initially applied to the device. The Watchdog timer can act as an oscillator fail
detect because it uses an independent, fully on-chip oscillator.
The external reset input is disabled, and fully internal reset generation enabled, by
programming the RPD bit in the EPROM configuration register UCFG1 to 0. EPROM
configuration is described in Section 8.18 “EPROM characteristics” on page 66.
4 POF Power-on Flag. Set automatically when a Power-on reset has
occurred. Cleared by software. Refer to the Section 8.11 “Power
monitoring functions” on page 42 for additional information.
3 GF1 General purpose flag 1. May be read or written by user software,
but has no effect on operation.
2 GF0 General purpose flag 0. May be read or written by user software,
but has no effect on operation.
1 PD Power-down control bit. Setting this bit activates Power-down
mode operation. Cleared when the Power-down mode is
terminated (see text).
0 IDL Idle mode control bit. Setting this bit activates Idle mode operation.
Cleared when the Idle mode is terminated (see text).
Table 42: PCON - Power control register (address 87H) bit description
…continued
Bit Symbol Description
Fig 17. Typical external reset circuits.
002aaa635
87LPC778
P1.5
87LPC778
RST
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P79

P87LPC778FDH,529

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NXP Semiconductors
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IC MCU 8BIT 8KB OTP 20TSSOP
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