P87LPC778FDH,529 Datasheet P87LPC778FDH,529 | P55-P57

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data Rev. 01 — 31 March 2004 55 of 79

9397 750 12378

RECEIVE enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT

CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of

every machine cycle in which RECEIVE is active, the contents of the receive shift

the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle.

As data bits come in from the right, ‘1’s shift out to the left. When the ‘0’ that was

initially loaded into the rightmost position arrives at the leftmost position in the shift

the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared

as RI is set.

8.15.9 More about UART Mode 1

Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0),

8 data bits (LSB ﬁrst), and a stop bit (1). On receive, the stop bit goes into RB8 in

SCON. In the P87LPC778 the baud rate is determined by the Timer1 overﬂow rate.

Figure 24 shows a simpliﬁed functional diagram of the serial port in Mode 1, and

associated timings for transmit receive.

Transmission is initiated by any instruction that uses SBUF as a destination register.

The ‘write to SBUF’ signal also loads a ‘1’ into the 9th bit position of the transmit shift

actually commences at S1P1 of the machine cycle following the next rollover in the

divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16

counter, not to the ‘write to SBUF’ signal.)

The transmission begins with activation of SEND which puts the start bit at TxD. One

bit time later, DATA is activated, which enables the output bit of the transmit shift

As data bits shift out to the right, zeros are clocked in from the left. When the MSB of

the data byte is at the output position of the shift register, then the ‘1’ that was initially

loaded into the 9th position is just to the left of the MSB, and all positions to the left of

that contain zeros. This condition ﬂags the TX Control unit to do one last shift and

then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after

‘write to SBUF.’

Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is

sampled at a rate of 16 times whatever baud rate has been established. When a

transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is

written into the input shift register. Resetting the divide-by-16 counter aligns its

rollovers with the boundaries of the incoming bit times.

The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th

counter states of each bit time, the bit detector samples the value of RxD. The value

accepted is the value that was seen in at least 2 of the 3 samples. This is done for

noise rejection. If the value accepted during the ﬁrst bit time is not ‘0’, the receive

circuits are reset and the unit goes back to looking for another 1-to-0 transition. This

is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the

input shift register, and reception of the rest of the frame will proceed.

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data Rev. 01 — 31 March 2004 56 of 79

9397 750 12378

As data bits come in from the right, 1s shift out to the left. When the start bit arrives at

the leftmost position in the shift register (which in mode 1 is a 9-bit register), it ﬂags

the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal

to load SBUF and RB8, and to set RI, will be generated if, and only if, the following

conditions are met at the time the ﬁnal shift pulse is generated:

1. R1 = 0, and

2. Either SM2 = 0, or the received stop bit = 1.

If either of these two conditions is not met, the received frame is irretrievably lost. If

both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and

RI is activated. At this time, whether the above conditions are met or not, the unit

goes back to looking for a 1-to-0 transition in RxD.

8.15.10 More about UART Modes 2 and 3

Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8

data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (1). On transmit, the

9th data bit (TB8) can be assigned the value of ‘0’ or ‘1’. On receive, the 9th data bit

goes into RB8 in SCON. The baud rate is programmable to either

⁄

of the

CPU clock frequency in Mode 2. Mode 3 may have a variable baud rate generated

from Timer1.

Figures 25 and 26 show a functional diagram of the serial port in Modes 2 and 3. The

receive portion is exactly the same as in Mode 1. The transmit portion differs from

Mode 1 only in the 9th bit of the transmit shift register.

Transmission is initiated by any instruction that uses SBUF as a destination register.

The ‘write to SBUF’ signal also loads TB8 into the 9th bit position of the transmit shift

commences at S1P1 of the machine cycle following the next rollover in the

divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16

counter, not to the ‘write to SBUF’ signal.)

The transmission begins with activation of SEND, which puts the start bit at TxD. One

bit time later, DATA is activated, which enables the output bit of the transmit shift

a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are

clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left.

When TB8 is at the output position of the shift register, then the stop bit is just to the

left of TB8, and all positions to the left of that contain zeros. This condition ﬂags the

TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs

at the 11th divide-by-16 rollover after ‘write to SBUF.’

Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is

sampled at a rate of 16 times whatever baud rate has been established. When a

transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is

written to the input shift register.

At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the

value of R-D. The value accepted is the value that was seen in at least 2 of the 3

samples. If the value accepted during the ﬁrst bit time is not ‘0’, the receive circuits

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data Rev. 01 — 31 March 2004 57 of 79

9397 750 12378

are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit

proves valid, it is shifted into the input shift register, and reception of the rest of the

frame will proceed.

As data bits come in from the right, 1s shift out to the left. When the start bit arrives at

the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it

ﬂags the RX Control block to do one last shift, load SBUF and RB8, and set RI.

The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the

following conditions are met at the time the ﬁnal shift pulse is generated. 1. RI = 0,

and 2. Either SM2 = 0, or the received 9th data bit = 1.

If either of these conditions is not met, the received frame is irretrievably lost, and RI

is not set. If both conditions are met, the received 9th data bit goes into RB8, and the

ﬁrst 8 data bits go into SBUF. One bit time later, whether the above conditions were

met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input.

8.15.11 Multiprocessor communications

UART modes 2 and 3 have a special provision for multiprocessor communications. In

these modes, 9 data bits are received or transmitted. When data is received, the 9th

bit is stored in RB8. The UART can be programmed such that when the stop bit is

received, the serial port interrupt will be activated only if RB8 = 1. This feature is

enabled by setting bit SM2 in SCON. One way to use this feature in multiprocessor

systems is as follows:

When the master processor wants to transmit a block of data to one of several slaves,

it ﬁrst sends out an address byte which identiﬁes the target slave. An address byte

differs from a data byte in that the 9th bit is ‘1’ in an address byte and ‘0’ in a data

byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte,

however, will interrupt all slaves, so that each slave can examine the received byte

and see if it is being addressed. The addressed slave will clear its SM2 bit and

prepare to receive the data bytes that follow. The slaves that weren’t being addressed

leave their SM2 bits set and go on about their business, ignoring the subsequent data

bytes.

SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the

stop bit, although this is better done with the Framing Error ﬂag. In a Mode 1

reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit

is received.

8.15.12 Automatic address recognition

Automatic Address Recognition is a feature which allows the UART to recognize

certain addresses in the serial bit stream by using hardware to make the

comparisons. This feature saves a great deal of software overhead by eliminating the

need for the software to examine every serial address which passes by the serial

port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART

modes, mode 2 and mode 3, the Receive Interrupt ﬂag (RI) will be automatically set

when the received byte contains either the ‘Given’ address or the ‘Broadcast’

address. The 9 bit mode requires that the 9th information bit is a ‘1’ to indicate that

the received information is an address and not data.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P69 P70-P72 P73-P75 P76-P78 P79-P79

P87LPC778FDH,529

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NXP Semiconductors

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IC MCU 8BIT 8KB OTP 20TSSOP

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