P87LPC778FDH,529 Datasheet P87LPC778FDH,529 | P31-P33

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data Rev. 01 — 31 March 2004 31 of 79

9397 750 12378

Values to be used in the CT1 and CT0 bits are shown in Table 3 0. To allow the

C-bus to run at the maximum rate for a particular oscillator frequency, compare the

actual oscillator rate to the f

osc

max column in the table. The value for CT1 and CT0 is

found in the ﬁrst line of the table where CPU clock max is greater than or equal to the

actual frequency. Tabl e 30 also shows the machine cycle count for various settings of

CT1/CT0. This allows calculation of the actual minimum high and low times for SCL

as follows:

(5)

For instance, at an 8 MHz frequency, with CT1/CT0 set to 1 0, the minimum SCL high

and low times will be 5.25 µs. Ta ble 3 0 also shows the Timer I timeout period (given

in machine cycles) for each CT1/CT0 combination. The timeout period varies

because of the way in which minimum SCL high and low times are measured. When

the I

C-bus interface is operating, Timer I is pre-loaded at every SCL transition with a

value dependent upon CT1/CT0. The pre-load value is chosen such that a minimum

SCL high or low time has elapsed when Timer I reaches a count of 008 (the actual

value pre-loaded into Timer I is 8 minus the machine cycle count).

Table 27: I2CFG - I

C-bus conﬁguration register (address C8h) bit allocation

Not bit addressable; Reset value: 00H

Bit 7 6 5 4 3 2 1 0

Symbol SLAVEN MASTRQ CLRTI TIRUN - - CT1 CT0

Table 28: I2CFG - I

C-bus conﬁguration register (address C8h) bit description

Bit Symbol Description

7 SLAVEN Slave Enable. Writing a ‘1’ this bit enables the slave functions of

the I

C-bus subsystem. If SLAVEN and MASTRQ are ‘0’, the

C-bus hardware is disabled. This bit is cleared to ‘0’ by reset and

by an I

C-bus time-out.

6 MASTRQ Master Request. Writing a ‘1’ to this bit requests mastership of the

C-bus. If a transmission is in progress when this bit is changed

from ‘0’ to ‘1’, action is delayed until a stop condition is detected. A

start condition is sent and DRDY is set (thus making ATN = 1 and

generating an I

C-bus interrupt). When a master wishes to release

mastership status of the I

C-bus, it writes a ‘1’ to XSTP in I2CON.

MASTRQ is cleared by an I

C-bus time-out.

5 CLRTI Writing a ‘1’ to this bit clears the Timer I overﬂow ﬂag. This bit

position always reads as a ‘0’.

4 TIRUN Writing a ‘1’ to this bit lets Timer I run; a ‘0’ stops and clears it.

Together with SLAVEN, MASTRQ, and MASTER, this bit

determines operational modes as shown in Tabl e 2 9.

3, 2 - Reserved for future use. Should not be set to ‘1’ by user programs.

1, 0 CT1, CT0 These two bits are programmed as a function of the CPU clock

rate, to optimize the MIN HI and LO time of SCL when this device

is a master on the I

C-bus. The time value determined by these

bits controls both of these parameters, and also the timing for stop

and start conditions.

SCL min high/low time (in microseconds)

6 * min time count

CPUclock (in MHz)

------------------------------------------------

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data Rev. 01 — 31 March 2004 32 of 79

9397 750 12378

8.8 Interrupts

The P87LPC778 uses a four priority level interrupt structure. This allows great

ﬂexibility in controlling the handling of the P87LPC778’s many interrupt sources. The

P87LPC778 supports up to 13 interrupt sources.

Each interrupt source can be individually enabled or disabled by setting or clearing a

bit in registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA,

which disables all interrupts at once.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the IP0, IP0H, IP1, and IP1H registers. An interrupt service

routine in progress can be interrupted by a higher priority interrupt, but not by another

interrupt of the same or lower priority. The highest priority interrupt service cannot be

interrupted by any other interrupt source. So, if two requests of different priority levels

are received simultaneously, the request of higher priority level is serviced.

If requests of the same priority level are received simultaneously, an internal polling

sequence determines which request is serviced. This is called the arbitration ranking.

Note that the arbitration ranking is only used to resolve simultaneous requests of the

same priority level.

Table 29: Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER

SLAVEN,

MASTRQ,

MASTER

TIRUN OPERATING MODE

All 0 0 The I

C-bus interface is disabled. Timer I is cleared and

does not run. This is the state assumed after a reset. If

an I

C-bus application wants to ignore the I

C-bus at

certain times, it should write SLAVEN, MASTRQ, and

TIRUN all to zero.

All 0 1 The I

C-bus interface is disabled.

Any or all 1 0 The I

C-bus interface is enabled. The 3 low-order bits

of Timer I run for min-time generation, but the hi-order

bits do not, so that there is no checking for I

C-bus

being ‘hung.’ This conﬁguration can be used for very

slow I

C-bus operation.

Any or all 1 1 The I

C-bus interface is enabled. Timer I runs during

frames on the I

C-bus, and is cleared by transitions on

SCL, and by Start and Stop conditions. This is the

normal state for I

C-bus operation.

Table 30: CT1, CT0 values

CT1, CT0 Min Time Count

(Machine Cycles)

CPU Clock Max

(for 100 kHz I

C-bus)

Timeout Period

(Machine Cycles)

1 0 7 8.4 MHz 1023

0 1 6 7.2 MHz 1022

0 0 5 6.0 MHz 1021

1 1 4 4.8 MHz 1020

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data Rev. 01 — 31 March 2004 33 of 79

9397 750 12378

Table 3 1 summarizes the interrupt sources, ﬂag bits, vector addresses, enable bits,

priority bits, arbitration ranking, and whether each interrupt may wake up the CPU

from Power-down mode.

8.8.1 External interrupt inputs

The P87LPC778 has two individual interrupt inputs as well as the Keyboard Interrupt

function. The latter is described separately elsewhere in this section. The two

interrupt inputs are identical to those present on the standard 80C51 microcontroller.

The external sources can be programmed to be level-activated or transition-activated

by setting or clearing bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is

triggered by a detected low at the INTn pin. If ITn = 1, external interrupt n is edge

triggered. In this mode if successive samples of the INTn pin show a high in one cycle

and a low in the next cycle, interrupt request ﬂag IEn in TCON is set, causing an

interrupt request.

Since the external interrupt pins are sampled once each machine cycle, an input high

or low should hold for at least 6 CPU Clocks to ensure proper sampling. If the

external interrupt is transition-activated, the external source has to hold the request

pin high for at least one machine cycle, and then hold it low for at least one machine

cycle. This is to ensure that the transition is seen and that interrupt request ﬂag IEn is

set. IEn is automatically cleared by the CPU when the service routine is called.

If the external interrupt is level-activated, the external source must hold the request

active until the requested interrupt is actually generated. If the external interrupt is still

asserted when the interrupt service routine is completed another interrupt will be

generated. It is not necessary to clear the interrupt ﬂag IEn when the interrupt is level

sensitive, it simply tracks the input pin level.

If an external interrupt is enabled when the P87LPC778 is put into Power-down or

Idle mode, the interrupt will cause the processor to wake up and resume operation.

Refer to Section 8.12 “Power reduction modes” on page 43 for details.

Table 31: Summary of interrupts

Description Interrupt

Flag Bit(s)

Vector

Address

Interrupt

Enable Bit(s)

Interrupt

Priority

Arbitration

Ranking

Power-down

Wake-up

External Interrupt 0 IE0 0003h EX0 (IEN0.0) IP0H.0, IP0.0 1 (highest) Yes

Timer0 Interrupt TF0 000Bh ET0 (IEN0.1) IP0H.1, IP0.1 4 No

External Interrupt 1 IE1 0013h EX1 (IEN0.2) IP0H.2, IP0.2 7 Yes

Timer1 Interrupt TF1 001Bh ET1 (IEN0.3) IP0H.3, IP0.3 10 No

Serial Port Tx and Rx TI & RI 0023h ES (IEN0.4) IP0H.4, IP0.4 12 No

Brownout Detect BOD 002Bh EBO (IEN0.5) IP0H.5, IP0.5 2 Yes

C-bus Interrupt ATN 0033h EI2 (IEN1.0) IP1H.0, IP1.0 5 No

KBI Interrupt KBF 003Bh EKB (IEN1.1) IP1H.1, IP1.1 8 Yes

Comparator 2 interrupt CMF2 0043h EC2 (IEN1.2) IP1H.2, IP1.2 11 Yes

Watchdog Timer WDOVF 0053h EWD (IEN0.6) IP0H.6, IP0.6 3 Yes

A/D Converter ADCI 005Bh EAD (IEN1.4) IP1H.4, IP1.4 6 Yes

Comparator 1 interrupt CMF1 0063h EC1 (IEN1.5) IP1H.5, IP1.5 9 Yes

Timer I interrupt - 0073h ETI (IEN1.7) IP1H.7, IP1.7 13 (lowest) No

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P87LPC778FDH,529

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