Philips Semiconductors
P87LPC778
CMOS single-chip 8-bit microcontroller
Product data Rev. 01 — 31 March 2004 63 of 79
9397 750 12378
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.16 Watchdog timer
When enabled via the WDTE configuration bit, the Watchdog timer is operated from
an independent, fully on-chip oscillator in order to provide the greatest possible
dependability. When the Watchdog feature is enabled, the timer must be fed regularly
by software in order to prevent it from resetting the CPU, and it cannot be turned off.
When disabled as a Watchdog timer (via the WDTE bit in the UCFG1 configuration
register), it may be used as an interval timer and may generate an interrupt. The
Watchdog timer is shown in Figure 27.
The Watchdog timeout time is selectable from one of eight values, nominal times
range from 16 milliseconds to 2.1 seconds. The frequency tolerance of the
independent Watchdog RC oscillator is ±37 %. The timeout selections and other
control bits are shown in Tables 55 and 56. When the Watchdog function is enabled,
the WDCON register may be written once during chip initialization in order to set the
Watchdog timeout time. The recommended method of initializing the WDCON
register is to first feed the Watchdog, then write to WDCON to configure the WDS[2:0]
bits. Using this method, the Watchdog initialization may be done any time within 10
milliseconds after start-up without a Watchdog overflow occurring before the
initialization can be completed.
Since the Watchdog timer oscillator is fully on-chip and independent of any external
oscillator circuit used by the CPU, it intrinsically serves as an oscillator fail detection
function. If the Watchdog feature is enabled and the CPU oscillator fails for any
reason, the Watchdog timer will time out and reset the CPU.
When the Watchdog function is enabled, the timer is deactivated temporarily when a
chip reset occurs from another source, such as a Power-on reset, brownout reset, or
external reset.
Fig 27. Block diagram of the Watchdog timer.
002aaa645
500 kHz
R/C OSCILLATOR
CLOCK OUT
ENABLE
WDCLK * WDTE
WDTE + WDRUN
state clock
20-BIT COUNTER
CLEAR
8 MSBs
WDS2-0
(WDCON.2-0)
WDTE (UCFG1.7)
watchdog
reset
watchdog
interrupt
WDOVF
(WDCON.5)
WATCHDOG
FEED DETECT
BOD (xxx.x)
POR (xxx.x)
S
R
Q
8 TO 1 MUX
