Philips Semiconductors
P87LPC778
CMOS single-chip 8-bit microcontroller
Product data Rev. 01 — 31 March 2004 27 of 79
9397 750 12378
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
• The MINIMUM SCL HIGH TO SDA HIGH time in a stop condition.
• The MINIMUM SDA HIGH TO SDA LOW time between I
2
C-bus stop and start
conditions (4.7 ms, see I
2
C-bus specification).
• The MINIMUM SDA LOW TO SCL LOW time in a start condition.
The MAXIMUM SCL CHANGE time while an I
2
C-bus frame is in progress. A frame is
in progress between a start condition and the following stop condition. This time span
serves to detect a lack of software response on this device as well as external
I
2
C-bus problems. SCL ‘stuck low’ indicates a faulty master or slave. SCL ‘stuck high’
may mean a faulty device, or that noise induced onto the I
2
C-bus caused all masters
to withdraw from I
2
C-bus arbitration.
The first five of these times are 4.7 ms (see I
2
C-bus specification) and are covered by
the low order three bits of Timer I. Timer I is clocked by the 87LPC77987 CPU clock.
Timer I can be pre-loaded with one of four values to optimize timing for different
oscillator frequencies. At lower frequencies, software response time is increased and
will degrade maximum performance of the I
2
C-bus. See special function register
I2CFG description for prescale values (CT0, CT1).
The MAXIMUM SCL CHANGE time is important, but its exact span is not critical. The
complete 10 bits of Timer I are used to count out the maximum time. When I
2
C-bus
operation is enabled, this counter is cleared by transitions on the SCL pin. The timer
does not run between I
2
C-bus frames (i.e., whenever reset or stop occurred more
recently than the last start). When this counter is running, it will carry out after 1020 to
1023 machine cycles have elapsed since a change on SCL. A carry out causes a
hardware reset of the I
2
C-bus interface. In cases where the bus hang-up is due to a
lack of software response by this device, the reset releases SCL and allows I
2
C-bus
operation among other devices to continue.
8.7.1 I
2
C-bus interrupts
If I
2
C-bus interrupts are enabled (EA and EI2 are both set to 1), an I
2
C-bus interrupt
will occur whenever the ATN flag is set by a start, stop, arbitration loss, or data ready
condition (refer to the description of ATN following). In practice, it is not efficient to
operate the I
2
C-bus interface in this fashion because the I
2
C-bus interrupt service
routine would somehow have to distinguish between hundreds of possible conditions.
Also, since I
2
C-bus can operate at a fairly high rate, the software may execute faster if
the code simply waits for the I
2
C-bus interface.
Typically, the I
2
C-bus interrupt should only be used to indicate a start condition at an
idle slave device, or a stop condition at an idle master device (if it is waiting to use the
I
2
C-bus). This is accomplished by enabling the I
2
C-bus interrupt only during the
aforementioned conditions.
[1] Due to the manner in which bit addressing is implemented in the 80C51 family, the I2CON register
should never be altered by use of the SETB, CLR, CPL, MOV (bit), or JBC instructions. This is due to
the fact that read and write functions of this register are different. Testing of I2CON bits via the JB and
JNB instructions is supported.
Table 23: I2CON - I
2
C-bus control register (address D8H) bit allocation
Bit addressable
[1]
; Reset value: 81H
Bit 7 6 5 4 3 2 1 0
Symbol (R) RDAT ATN DRDY ARL STR STP MASTER -
Symbol (W) CXA IDLE CDR CARL CSTR CSTP XSTR XSTP
