Philips Semiconductors
P87LPC778
CMOS single-chip 8-bit microcontroller
Product data Rev. 01 — 31 March 2004 29 of 79
9397 750 12378
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ARL — ‘Arbitration Loss’ is ‘1’ when transmit Active was set, but this device lost
arbitration to another transmitter. Transmit Active is cleared when ARL is ‘1’. There
are four separate cases in which ARL is set:
1. If the program sent a ‘1’ or repeated start, but another device sent a ‘0’, or a stop,
so that SDA is ‘0’ at the rising edge of SCL. (If the other device sent a stop, the
setting of ARL will be followed shortly by STP being set.)
2. If the program sent a ‘1’, but another device sent a repeated start, and it drove
SDA LOW before SCL could be driven LOW. (This type of ARL is always
accompanied by STR = 1.)
3. In master mode, if the program sent a repeated start, but another device sent a
‘1’, and it drove SCL LOW before this device could drive SDA LOW.
4. In master mode, if the program sent stop, but it could not be sent because
another device sent a ‘0’.
STR — ‘STaRt’ is set to a ‘1’ when an I
2
C-bus start condition is detected at a non-idle
slave or at a master. (STR is not set when an idle slave becomes active due to a start
bit; the slave has nothing useful to do until the rising edge of SCL sets DRDY.)
STP — ‘SToP’ is set to 1 when an I
2
C-bus stop condition is detected at a non-idle
slave or at a master. (STP is not set for a stop condition at an idle slave.)
MASTER — ‘MASTER’ is ‘1’ if this device is currently a master on the I
2
C-bus.
MASTER is set when MASTRQ is ‘1’ and the bus is not busy (i.e., if a start bit hasn’t
been received since reset or a ‘Timer I’ time-out, or if a stop has been received since
the last start). MASTER is cleared when ARL is set, or after the software writes
MASTRQ = 0 and then XSTP = 1.
8.7.4 Writing I2CON
Typically, for each bit in an I
2
C-bus message, a service routine waits for ATN = 1.
Based on DRDY, ARL, STR, and STP, and on the current bit position in the message,
it may then write I2CON with one or more of the following bits, or it may read or write
the I2DAT register.
CXA — Writing a ‘1’ to ‘Clear Xmit Active’ clears the Transmit Active state. (Reading
the I2DAT register also does this.)
8.7.5 Regarding Transmit Active
Transmit Active is set by writing the I2DAT register, or by writing I2CON with
XSTR = 1 or XSTP = 1. The I
2
C-bus interface will only drive the SDA line low when
Transmit Active is set, and the ARL bit will only be set to ‘1’ when Transmit Active is
set. Transmit Active is cleared by reading the I2DAT register, or by writing I2CON with
CXA = 1. Transmit Active is automatically cleared when ARL is ‘1’.
IDLE — Writing ‘1’ to ‘IDLE’ causes a slave’s I
2
C-bus hardware to ignore the I
2
C-bus
until the next start condition (but if MASTRQ is ‘1’, then a stop condition will cause
this device to become a master).
CDR — Writing a ‘1’ to ‘Clear Data Ready' clears DRDY. (Reading or writing the
I2DAT register also does this.)
CARL — Writing a ‘1’ to ‘Clear Arbitration Loss’ clears the ARL bit.
CSTR — Writing a ‘1’ to ‘Clear STaRt’ clears the STR bit.
