PCA9665_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 August 2008 11 of 90
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
Remark: ENSIO bit value must be changed only when the I
2
C-bus is idle.
7.3.1.5 The indirect data field access register, INDIRECT (A1 = 1, A0 = 0)
The registers in the indirect address space can be accessed using the INDIRECT data
field. Before writing or reading such a register, the INDPTR register should be written with
the address of the indirect register that needs to be accessed. Once the INDPTR register
contains the appropriate value, reads and writes to the INDIRECT data field will actually
read and write the selected indirect register.
5 STA The START flag.
STA = 1: When the STA bit is set to enter a master mode, the bus controller
hardware checks the status of the I
2
C-bus and generates a START condition if the
bus is free. If the bus is not free, then the bus controller waits for a STOP condition
(which will free the bus) and generates a START condition after the minimum
buffer time (t
BUF
) has elapsed.
If STA is set while the bus controller is already in a master mode and one or more
bytes are transmitted or received, the bus controller transmits a repeated START
condition. STA may be set at any time. STA may also be set when the bus
controller is an addressed slave. A START condition will then be generated after a
STOP condition and the minimum buffer time (t
BUF
) has elapsed.
STA = 0: When the STA bit is reset, no START condition or repeated START
condition will be generated.
4 STO The STOP flag.
STO = 1: When the STO bit is set while the bus controller is in a master mode, a
STOP condition is transmitted on the I
2
C-bus. When a STOP condition is detected
on the bus, the hardware clears the STO flag.
If the STA and STO bits are both set and the PCA9665 is in master mode, then a
STOP condition is transmitted on the I
2
C-bus. The bus controller then transmits a
START condition after the minimum buffer time (t
BUF
) has elapsed.
STO=0: When the STO bit is reset, no STOP condition will be generated.
3 SI The Serial Interrupt flag.
SI = 1: When the SI flag is set, and, if the ENSIO bit is also set, a serial interrupt is
requested. SI is set by hardware when one of 29 of the 30 possible states of the
bus controller states is entered. The only state that does not cause SI to be set is
state F8h, which indicates that no relevant state information is available.
While SI is set, the LOW period of the serial clock on the SCL line is stretched,
and the serial transfer is suspended. A HIGH level on the SCL line is unaffected
by the serial interrupt flag. SI is automatically cleared when the I2CCON register
is written. The SI bit cannot be set by the user.
SI = 0: When the SI flag is reset, no serial interrupt is requested, and there is no
stretching of the serial clock on the SCL line.
2:1 - Reserved. When I2CCON is read, zeroes are read. Must be written with zeroes.
0 MODE The Mode flag.
MODE = 0; Byte mode. See
Section 8.1.1 “Byte mode” for more detail.
MODE = 1; buffered mode. See
Section 8.1.2 “Buffered mode” for more detail.
Table 12. I2CCON - Control register (A1 = 1, A0 = 1) bit description
…continued
Bit Symbol Description
