PCA9665N,112 Datasheet PCA9665N,112 | P49-P51

Product data sheet Rev. 03 — 12 August 2008 49 of 90

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

3. Program I2CCON register to initiate the Master Receiver Buffered sequence. In

Master mode, if STA = 1, a START command is sent. An interrupt will be asserted and

the SI bit is set in the I2CCON register after the START has been sent. The I2CSTA

a write to the I2CCON register is performed.

4. After reading the I2CSTA status register, the I2CCON is programmed with STA = 0.

That clears the previous Interrupt. If a START command has been previously sent, the

C-bus address + R/W = 1 byte that has been loaded into the buffer is sent to the

C-bus, the PCA9665 then becomes a master receiver device and starts receiving

data from the addressed slave device.

Remark: The PCA9665 is already a master receiver device if a buffered sequence

has been previously executed.

5. When the sequence has been executed, an Interrupt is asserted and the SI bit is set

in the I2CCON register. The I2CSTA register contains the status of the transmission

and the I2CCOUNT register contains the number of bytes that have been received.

I2CDAT buffer contains all the data that has been received and can be read by the

microcontroller.

6. More sequences (program the I2CCOUNT register, write to the I2CCON register, read

the I2CSTA register when sequence has been executed, read the I2CDAT buffer) can

be performed as long as a STOP or a Repeated START command has not been sent.

To be able to end the reception, the last buffered sequence must be performed with

LB = 1. Master Receiver Buffered mode ends when the I2CCOUNT register is

programmed with STO = 1.

8.5.3 Buffered Slave Transmitter mode

1. An interrupt is asserted and the SI bit is set in the I2CCON register when the

PCA9665’s own slave address has been detected on the I

C-bus (AA = 1, own slave

address deﬁned in the I2CADR register). In Slave Transmitter mode, R/W=1.

2. Program the I2CCOUNT register with the number of bytes that need to be sent to the

C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used for Receiver Buffered

mode only.

3. Load the data bytes in I2CDAT buffer. The different bytes to be sent will be stored in

the PCA9665 buffer. There is no protection against writing over a buffer’s boundary. If

more than 68 bytes are written to the buffer, the data at address 00h will be

overwritten. The number of bytes that needs to be loaded in I2CDAT is equal to

BC[6:0] in the I2CCOUNT register. The number of data bytes sent is equal to BC[6:0],

therefore, if the number of data bytes loaded is greater than BC[6:0], the additional

data will not be sent. If the number of data bytes written to the buffer is less than

BC[6:0], the PCA9665 will still send out BC[6:0] data bytes.

4. The I2CCON is programmed to clear the previous Interrupt. The bytes loaded into the

buffer are sent to the I

C-bus. MODE bits must be set to ‘1’ each time a write to the

I2CCON register is performed.

5. When the sequence has been executed (BC[6:0] bytes sent or the master sent a

NACK), an Interrupt is asserted and the SI bit is set in the I2CCON register. The

I2CSTA register contains the status of the transmission and the I2CCOUNT register

contains the number of bytes that have been sent to the I

C-bus.

Product data sheet Rev. 03 — 12 August 2008 50 of 90

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

6. More sequences (program I2CCOUNT register, load data bytes in I2CDAT buffer,

write the I2CCON register to send the data to the I

C-bus, read the I2CSTA register

when sequence has been executed) can be performed as long as the master

acknowledges the bytes sent by the PCA9665 and AA = 1. Slave Transmitter Buffered

mode ends when the I

C-bus master does not acknowledge a byte or when the

PCA9665 goes to Non-addressed Slave mode.

8.5.4 Buffered Slave Receiver mode

1. An interrupt is asserted and the SI bit is set in the I2CCON register when the

PCA9665‘s own slave address has been detected in the I

C-bus (AA = 1, own slave

address deﬁned in the I2CADR register). In Slave Receiver mode, R/W=0.

2. Program the I2CCOUNT register with the number of bytes that needs to be read from

a master device in the I

C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used in

Receiver mode to let the PCA9665 know if the last byte received must be

acknowledged or not.

LB = 0: Last received byte is acknowledged and another sequence can be executed.

LB = 1: Last received byte is not acknowledged.

3. The I2CCON is programmed to clear the previous Interrupt. The PCA9665 receives

data from the I

C-bus master. MODE bit must be set to ‘1’ each time a write to the

I2CCON register is performed.

4. When the sequence has been executed (BC[6:0] bytes have been received or the

master sent a STOP or Repeated START command), an Interrupt is asserted and the

SI bit is set in the I2CCON register. The I2CSTA register contains the status of the

transmission and the I2CCOUNT register contains the number of bytes that have

been received. I2CDAT buffer contains all the data that has been received and can be

read by the microcontroller.

5. More sequence (program the I2CCOUNT register, write to the I2CCON register, read

the I2CDAT buffer) can be performed as long as a STOP or a Repeated START

command has not been sent by the I

C-bus master. Slave Receiver Buffered mode

ends when the I

C-bus master sends a STOP or Repeated START command, or

when the PCA9665 does not acknowledge the received bytes any more.

8.5.5 Example: Read 128 bytes in two 64-byte sequences of an EEPROM

C-bus address = A0h for write operations and A1h for read operations)

starting at Location 08h

1. Program I2CCOUNT = 02h (2 bytes to be sent): I

C-bus slave address and memory

allocation.

2. Write A0h (I

C-bus slave address and write command) and 08h (Location) into the

I2CDAT register.

3. Program I2CCON with STA = 1, STO = SI = 0, MODE = 1.

– the PCA9665 sends a START command

– the PCA9665 sends an interrupt, sets SI = 1 and updates I2CSTA register

– I2CSTA reads 08h

4. Program I2CCON with STA = STO = SI = 0, MODE = 1.

– I

C-bus slave address A0h, then EEPROM sub address 08h is sent on the bus

Product data sheet Rev. 03 — 12 August 2008 51 of 90

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

– the SCL line is held LOW by the PCA9665 after the 2 bytes have been sent

– the PCA9665 sends an Interrupt, sets SI = 1 and updates I2CSTA register

– I2CSTA reads 28h

5. Program I2CCOUNT = 40h (64 bytes to read and Last byte acknowledged).

6. Load I2CDAT with A1h (I

C-bus slave address and Read command).

7. Program I2CCON with STA = 1, SI = 0, MODE = 1.

– the PCA9665 sends a ReSTART command

– an interrupt is asserted and the I2CSTA register is updated

– the I2CSTA register reads 10h

8. Program I2CCON with STA = STO = SI = 0, MODE = 1.

– address A1h is sent followed by a read of 64 data bytes

– the last data byte is acknowledged

– the SCL line is held LOW by the PCA9665 after the data is read

– the PCA9665 sends an interrupt and updates I2CSTA register

– I2CSTA reads 50h

9. The microcontroller reads the 64 data bytes from the PCA9665.

10. Program I2CCOUNT = C0h (64 bytes and Last byte is not acknowledged).

11. Program I2CCON with STA = STO = SI = 0, MODE = 1.

12. The PCA9665 reads 64 bytes and does not acknowledge the last byte.

– the PCA9665 sends an Interrupt and updates I2CSTA register

– the I2CSTA reads 58h

– the SCL line is held LOW by the PCA9665

– the slave should release the SDA line

13. The microcontroller reads the 64 bytes from the PCA9665.

14. Program I2CCON with SI = STA = 0, ST0 = 1, MODE = X.

– the PCA9665 sends a STOP condition

– no interrupt is generated by the PCA9665

– the I2CSTA register contains F8h

8.6 I2CCOUNT register

When a write to the I2CCOUNT register is requested, the buffer pointer is reset and points

at the ﬁrst byte. Loading of the data in the I2CDAT buffer then starts at the ﬁrst byte.

Once an operation has been performed (SI = 1 and an interrupt is generated), the

I2CCOUNT register contains the number of bytes that have been received (Receiver

mode) or the number of bytes that have been sent (Transmitter mode). See Table 42 for

more information.

In Buffered Transmitter mode, the ﬁrst byte that is sent to the I

C-bus is always the ﬁrst

byte that has been loaded in the I2CDAT buffer.

PCA9665N,112

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