PCA9665_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 August 2008 31 of 90
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
8.4 Buffered mode
8.4.1 Master Transmitter Buffered mode
In the Master Transmitter Buffered mode, a number of data bytes are transmitted to a
slave receiver several bytes at a time (see Figure 11). Before the Master Transmitter
Buffered mode can be entered, I2CCON must be initialized as shown in Table 33.
ENSIO must be set to logic 1 to enable the PCA9665. If the AA bit is reset, the PCA9665
will not acknowledge its own slave address in the event of another device becoming
master of the bus (in other words, if AA is reset, the PCA9665 cannot enter a slave mode).
STA, STO, and SI must be reset. Once ENSIO has been set to logic 1, it takes about
550 µs for the oscillator to start up.
The Master Transmitter Buffered mode may now be entered by setting the STA bit. The
I
2
C-bus state machine will first test the I
2
C-bus and generate a START condition as soon
as the bus becomes free. When a START condition is transmitted, the Serial Interrupt flag
(SI) is set, the Interrupt line (INT) goes LOW and the status code in the status register
(I2CSTA) will be 08h. This status code must be used to vector to an interrupt service
routine that loads I2CDAT with the slave address and the data direction bit (SLA+W)
followed by the number of data bytes to be sent. The byte count register (I2CCOUNT) has
been previously programmed with the number of bytes that need to be sent in a single
sequence (BC[6:0]) as shown in Table 34. LB bit is only used for the Receiver Buffered
modes and can be programmed to either logic 0 or logic 1. The total number of bytes
loaded in I2CDAT (slave address with direction bit plus data bytes) must be equal to the
value programmed in I2CCOUNT. A write to I2CCON resets the SI bit, clears the Interrupt
(INT goes HIGH) and allows the serial transfer to continue.
When the slave address with the direction bit and part of or all the following bytes have
been transmitted, the Serial Interrupt flag (SI) is set again, the Interrupt line (INT) goes
LOW again and I2CSTA is loaded with the following possible codes:
• 18h if an acknowledgment bit (ACK) has been received for the slave address with
direction bit (happens only if I2CCOUNT = 1; no data bytes have been sent).
• 20h if a no acknowledgment bit (NACK) has been received for the slave address with
direction bit (no data bytes have been sent).
• 28h if the slave address with direction bit and all the data bytes have been transmitted
and an acknowledgement bit has been received for each of them (number of bytes
sent is equal to value in I2CCOUNT).
Table 33. I2CCON initialization (Buffered mode)
Bit 7 6 5 4 3 2 1 0
Symbol AA ENSIO STA STO SI reserved reserved MODE
Value X1000XX1
Table 34. I2CCOUNT programming
Bit 7 6 5 4 3 2 1 0
Symbol LB BC6 BC5 BC4 BC3 BC2 BC1 BC0
Value X number of bytes received in a single sequence (1 byte to 68 bytes)
