PCA9665_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 August 2008 37 of 90
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
(1) See Table 28.
(2) No serial interrupt.
(3) Defined state when LB = 0 and the number of bytes received is equal to the value in I2CCOUNT register.
(4) Defined state when LB = 1 and the number of bytes received is equal to the value in I2CCOUNT register.
(5) Master Transmitter Byte mode is entered with MODE = 0. Master Transmitter Buffered mode is entered when MODE = 1.
Fig 12. Format and states in the Master Receiver Buffered mode (MODE = 1)
08h
S SLA R A
DATA
A P
50h F8h
MR
10h
S SLA R
W
to Master Transmitter mode
entry = MT
(5)
A P
48h F8h
002aab660
A
38h
other MST
continues
A or A
38h
other MST
continues
A
other MST
continues
successful
reception
from a Slave
Transmitter
next transfer
started with a
repeated START
condition
Not Acknowledge
received after
the slave address
arbitration lost in
slave address
or Acknowledge bit
arbitration lost and
addressed as slave
n
This number (contained in I2CSTA) corresponds
to a defined state of the I
2
C-bus.
(1)
DATA
A
any number of data bytes and
their associated Acknowledge bits
from master to slave
from slave to master
DATA A
58h
(3) (4)
B0h
68h
to corresponding states in Slave Transmitter mode
to corresponding states in Slave Receiver mode
D8h
to corresponding states in Slave Receiver mode (General Call)
(2)
DATA
A
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PCA9665_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 August 2008 38 of 90
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
Table 36. Master Receiver Buffered mode (MODE = 1)
Status
code
(I2CSTA)
Status of the
I
2
C-bus and the
PCA9665
Application software response Next action taken by the PCA9665
To/from I2CDAT To/from I2CCOUNT To I2CCON
LB BC[6:0] STA STO SI AA MODE
08h A START condition
has been transmitted
Load SLA+R 0 Total number of bytes
to be received
X X 0 X 1 SLA+R will be transmitted.
If ACK bit received, BC[6:0] data bytes will be
received, ACK bit will be returned for all of
them.
1 Total number of bytes
to be received
X X 0 X 1 SLA+R will be transmitted.
If ACK bit received, BC[6:0] data bytes will be
received, ACK bit will be returned for all of
them, except for the last one where NACK bit
will be returned.
10h A repeated START
condition has been
transmitted
Load SLA+R or 0 Total number of bytes
to be received
X X 0 X 1 SLA+R will be transmitted.
If ACK bit received, BC[6:0] data bytes will be
received, ACK bit will be returned for all of
them.
1 Total number of bytes
to be received
X X 0 X 1 SLA+R will be transmitted.
If ACK bit received, BC[6:0] data bytes will be
received, ACK bit will be returned for all of
them, except for the last one where NACK bit
will be returned.
Load SLA+W and
the data bytes
X Total number of bytes
to be transmitted
(= SLA+W + number
of data bytes)
X X 0 X 1 SLA+W will be transmitted;
PCA9665 will be switched to Master
Transmitter Buffered mode.
38h Arbitration lost in
NACK bit
No I2CDAT action
or
XX 0 0 0X1 I
2
C-bus will be released;
PCA9665 will enter slave mode.
No I2CDAT action X X 1 0 0 X 1 A START condition will be transmitted when
the bus becomes free.
48h SLA+R has been
transmitted;
NACK has been
received
No I2CDAT action
or
X X 1 0 0 X 1 Repeated START condition will be
transmitted.
No I2CDAT action
or
X X 0 1 0 X 1 STOP condition will be transmitted;
STO flag will be reset.
No I2CDAT action X X 1 1 0 X 1 STOP condition followed by a START
condition will be transmitted;
STO flag will be reset.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PCA9665_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 August 2008 39 of 90
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
50h BC[6:0] data bytes
have been received;
ACK has been
returned for all the
bytes
Read data bytes
or
0 Total number of bytes
to be received
0 0 0 X 1 BC[6:0] data bytes will be received, ACK bit
will be returned for all of them
Read data bytes
or
1 Total number of bytes
to be received
0 0 0 X 1 BC[6:0] data bytes will be received, ACK bit
will be returned for all of them, except for the
last one where NACK bit will be returned
58h BC[6:0] data bytes
have been received;
ACK has been
returned for all the
bytes, except for the
last one where NACK
bit has been returned
Read data bytes
or
X X 1 0 0 X 1 Repeated START condition will be transmitted
Read data bytes
or
X X 0 1 0 X 1 STOP condition will be transmitted;
STO flag will be reset.
Read data bytes X X 1 1 0 X 1 STOP condition followed by a START
condition will be transmitted;
STO flag will be reset.
Table 36. Master Receiver Buffered mode (MODE = 1)
…continued
Status
code
(I2CSTA)
Status of the
I
2
C-bus and the
PCA9665
Application software response Next action taken by the PCA9665
To/from I2CDAT To/from I2CCOUNT To I2CCON
LB BC[6:0] STA STO SI AA MODE

PCA9665N,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC CNTRLR PARALLEL/I2C 20-DIP
Lifecycle:
New from this manufacturer.
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