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PCA9665N,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84P85-P87P88-P90
PCA9665_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 August 2008 19 of 90
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
(1) See Table 27
(2) Defined state when a single byte is sent and an ACK is received.
(3) Defined state when a single byte is sent and a NACK is received.
(4) Master Receiver Byte mode is entered when MODE = 0. Master Receiver Buffered mode is entered when MODE = 1.
Fig 7. Format and states in the Master Transmitter Byte mode (MODE = 0)
08h
S SLA W A
DATA
A P
18h
28h F8h
MT
10h
S SLA W
R
to Master Receiver
mode entry = MR
(4)
A P
30h F8h
A P
20h F8h
002aab024
A or A
38h
other MST
continues
A or A
38h
other MST
continues
A
B0h
other MST
continues
68h
to corresponding states in Slave Transmitter mode
to corresponding states in Slave Receiver mode
successful
transmission
to a Slave Receiver
next transfer started with a
repeated START condition
Not Acknowledge received after
the slave address
Not Acknowledge received after
a data byte
arbitration lost in slave address
or data byte
arbitration lost and addressed as slave
n
This number (contained in I2CSTA) corresponds
to a defined state of the I
2
C-bus.
(1)
DATA
A
any number of data bytes and
their associated Acknowledge bits
from master to slave
from slave to master
D8h
to corresponding states in Slave Receiver mode (General Call)
(2)
(3)
PCA9665_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 August 2008 20 of 90
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
Table 27. Master Transmitter Byte mode (MODE = 0)
Status
code
(I2CSTA)
Status of the
I
2
C-bus and the
PCA9665
Application software response Next action taken by the PCA9665
To/from I2CDAT To I2CCON
STA STO SI AA MODE
08h A START condition
has been transmitted
Load SLA+W X X 0 X 0 SLA+W will be transmitted;
ACK/NACK will be received
10h A repeated START
condition has been
transmitted
Load SLA+W or X X 0 X 0 SLA+W will be transmitted;
ACK/NACK will be received
Load SLA+R X X 0 X 0 SLA+R will be transmitted;
PCA9665 will be switched to Master
Receiver Byte mode
18h SLA+W has been
transmitted; ACK has
been received
Load data byte or 0 0 0 X 0 Data byte will be transmitted;
ACK/NACK will be received
no I2CDAT action
or
1 0 0 X 0 Repeated START will be transmitted;
no I2CDAT action
or
0 1 0 X 0 STOP condition will be transmitted;
STO flag will be reset
no I2CDAT action 1 1 0 X 0 STOP condition followed by a START
condition will be transmitted;
STO flag will be reset
20h SLA+W has been
transmitted; NACK
has been received
Load data byte or 0 0 0 X 0 Data byte will be transmitted;
ACK/NACK will be received
no I2CDAT action
or
1 0 0 X 0 Repeated START will be transmitted;
no I2CDAT action
or
0 1 0 X 0 STOP condition will be transmitted;
STO flag will be reset
no I2CDAT action 1 1 0 X 0 STOP condition followed by a START
condition will be transmitted;
STO flag will be reset
28h Data byte in I2CDAT
has been transmitted;
ACK has been
received
Load data byte or 0 0 0 X 0 Data byte will be transmitted;
ACK/NACK will be received
no I2CDAT action
or
1 0 0 X 0 Repeated START will be transmitted;
no I2CDAT action
or
0 1 0 X 0 STOP condition will be transmitted;
STO flag will be reset
no I2CDAT action 1 1 0 X 0 STOP condition followed by a START
condition will be transmitted;
STO flag will be reset
PCA9665_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 August 2008 21 of 90
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
30h Data byte in I2CDAT
has been transmitted;
NACK has been
received
Load data byte or 0 0 0 X 0 Data byte will be transmitted;
ACK/NACK will be received
no I2CDAT action
or
1 0 0 X 0 Repeated START will be transmitted;
no I2CDAT action
or
0 1 0 X 0 STOP condition will be transmitted;
STO flag will be reset
no I2CDAT action 1 1 0 X 0 STOP condition followed by a START
condition will be transmitted;
STO flag will be reset
38h Arbitration lost in
SLA+W or Data bytes
No I2CDAT
action or
00000 I
2
C-bus will be released;
PCA9665 will enter Slave mode.
No I2CDAT
action or
00010 I
2
C-bus will be released;
PCA9665 will enter the Slave mode.
No I2CDAT
action
1 0 0 X 0 A START condition will be
transmitted when the bus becomes
free
Table 27. Master Transmitter Byte mode (MODE = 0)
…continued
Status
code
(I2CSTA)
Status of the
I
2
C-bus and the
PCA9665
Application software response Next action taken by the PCA9665
To/from I2CDAT To I2CCON
STA STO SI AA MODE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84P85-P87P88-P90

PCA9665N,112

Mfr. #:
Buy PCA9665N,112
Manufacturer:
NXP Semiconductors
Description:
IC CNTRLR PARALLEL/I2C 20-DIP
Lifecycle:
New from this manufacturer.
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