PCA9665N,112 Datasheet PCA9665N,112 | P58-P60

Product data sheet Rev. 03 — 12 August 2008 58 of 90

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

8.8.4 I2CSTA = 78h

This status code indicates that the SCL line is stuck LOW.

8.9 Some special cases

The PCA9665 has facilities to handle the following special cases that may occur during a

serial transfer.

8.9.1 Simultaneous repeated START conditions from two masters

A repeated START condition may be generated in the Master Transmitter or Master

Receiver modes. A special case occurs if another master simultaneously generates a

repeated START condition (see Figure 15). Until this occurs, arbitration is not lost by

either master since they were both transmitting the same data.

If the PCA9665 detects a repeated START condition on the I

C-bus before generating a

repeated START condition itself, it will use the repeated START as its own and continue

with the sending of the slave address.

8.9.2 Data transfer after loss of arbitration

Arbitration may be lost in the Master Transmitter and Master Receiver modes. Loss of

arbitration is indicated by the following states in I2CSTA; 38h, 68h, and B0h (see Figure 7,

Figure 11, Figure 8, and Figure 12).

Remark: In order to exit state 38h, a Time-out, Reset, or external STOP are required.

If the STA ﬂag in I2CCON is set by the routines which service these states, then, if the bus

is free again, a START condition (state 08h) is transmitted without intervention by the

CPU, and a retry of the total serial transfer can commence.

8.9.3 Forced access to the I

C-bus

In some applications, it may be possible for an uncontrolled source to cause a bus

hang-up. In such situations, the problem may be caused by interference, temporary

interruption of the bus or a temporary short-circuit between SDA and SCL.

If an uncontrolled source generates a superﬂuous START or masks a STOP condition,

then the I

C-bus stays busy indeﬁnitely. If the STA ﬂag is set and bus access is not

obtained within a reasonable amount of time, then a forced access to the I

C-bus is

possible. If the I

C-bus stays idle for a time period equal to the time-out period, then the

PCA9665 concludes that no other master is using the bus and sends a START condition.

Fig 15. Simultaneous repeated START conditions from 2 masters

S SLA W A

DATA

18h

28h

002aab028

other master sends

repeated START condition earlier

08h

both masters continue

with SLA transmission

Product data sheet Rev. 03 — 12 August 2008 59 of 90

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

8.9.4 I

C-bus obstructed by a LOW level on SCL or SDA

An I

C-bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the

SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is

possible, and the PCA9665 cannot resolve this type of problem. When this occurs, the

problem must be resolved by the device that is pulling the SCL bus line LOW.

When the SCL line stays LOW for a period equal to the time-out value, the PCA9665

concludes that this is a bus error and behaves in a manner described in Section 7.3.2.4

“The Time-out register, I2CTO (indirect address 04h)”.

If the SDA line is obstructed by another device on the bus (e.g., a slave device out of bit

synchronization), the problem can be solved by transmitting additional clock pulses on the

SCL line (see Figure 17). The PCA9665 sends out nine clock pulses followed by the

STOP condition. If the SDA line is released by the slave pulling it LOW, a normal START

condition is transmitted by the PCA9665, state 08h is entered and the serial transfer

continues. If the SDA line is not released by the slave pulling it LOW, then the PCA9665

concludes that there is a bus error, loads 70h in I2CSTA, generates an interrupt signal,

and releases the SCL and SDA lines. After the microcontroller reads the status register, it

needs to send a reset signal (hardware through the RESET pin, or software through the

parallel port) in order to reset the PCA9665. See Section 8.11 “Reset” for more

information.

If a forced bus access occurs or a repeated START condition is transmitted while SDA is

obstructed (pulled LOW), the PCA9665 performs the same action as described above. In

each case, state 08h is entered after a successful START condition is transmitted and

normal serial transfer continues. Note that the CPU is not involved in solving these bus

hang-up problems.

Fig 16. Forced access to a busy I

C-bus

STA flag

SDA line

SCL line

time-out

START condition

002aab029

Product data sheet Rev. 03 — 12 August 2008 60 of 90

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

8.9.5 Bus error

A bus error occurs when a START or STOP condition is present at an illegal position in the

format frame. Examples of illegal positions are during the serial transfer of an address

byte, a data or an acknowledge bit.

The PCA9665 only reacts to a bus error when it is involved in a serial transfer either as a

master or an addressed slave. When a bus error is detected, PCA9665 releases the SDA

and SCL lines, sets the interrupt ﬂag, and loads the status register with 00h. This status

code may be used to vector to a service routine which either attempts the aborted serial

transfer again or simply recovers from the error condition as shown in Table 46

“Miscellaneous states”. The microcontroller must send an external hardware or software

reset signal to reset the PCA9665.

8.10 Power-on reset

When power is applied to V

, an internal Power-On Reset holds the PCA9665 in a reset

condition until V

has reached V

POR

. At this point, the reset condition is released and the

PCA9665 goes to the power-up initialization phase where the following operations are

performed:

1. ENSIO bit is set to 1 to enable the internal oscillator.

2. Internal register initialization is performed.

3. ENSIO bit is set to 0 to disable the internal oscillator and go to the non-addressed low

power mode.

The complete power-up initialization phase takes 550 µs to be performed. During this

time, write to the PCA9665 through the parallel port is not permitted. However, the parallel

port can be read. This allows the device connected to the parallel port of the PCA9665 to

poll the I2CCON register and read the ENSIO state bit. When ENSIO bit is equal to 1, this

means that the power-up initialization is in progress. When ENSIO is set to 0, this means

that the power-up initialization is done and that the PCA9665 is initialized and ready to be

used.

Fig 17. Recovering from a bus obstruction caused by a LOW level on SDA

123456789

002aab030

STOP

condition

START

condition

STA flag

SDA line

SCL line

PCA9665N,112

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Manufacturer:

NXP Semiconductors

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IC CNTRLR PARALLEL/I2C 20-DIP

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