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PCA9665N,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84P85-P87P88-P90
PCA9665_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 August 2008 28 of 90
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
E0h Previously
addressed with
General Call; Data
has been received;
ACK has been
returned
Read data byte or X X 0 0 0 Data byte will be received and
NACK will be returned.
read data byte X X 0 1 0 Data byte will be received and ACK
will be returned.
E8h Previously
addressed with
General Call; Data
has been received;
NACK has been
returned
Read data byte or 0 X 0 0 0 Switched to not addressed slave
mode; no recognition of own slave
address or General Call address.
read data byte or 0 X 0 1 0 Switched to not addressed slave
mode; own slave address will be
recognized; General Call address
will be recognized if GC = 1.
read data byte or 1 0 0 0 0 Switched to not addressed slave
mode; no recognition of own slave
address or General Call address. A
START condition will be transmitted
when the bus becomes free.
read data byte 1 0 0 1 0 Switched to not addressed slave
mode; own slave address will be
recognized; General Call address
will be recognized if GC = 1. A
START condition will be transmitted
when the bus becomes free.
A0h A STOP condition or
repeated START
condition has been
received while still
addressed as Slave
Receiver
No I2CDAT action
or
0 X 0 0 0 Switched to not addressed slave
mode; no recognition of own slave
address or General Call address.
No I2CDAT action
or
0 X 0 1 0 Switched to not addressed slave
mode; Own slave address will be
recognized; General Call will be
recognized if GC = 1.
No I2CDAT action
or
1 X 0 0 0 Switched to not addressed slave
mode; no recognition of own slave
address or General Call. A START
condition will be transmitted when
the bus becomes free
No I2CDAT action 1 X 0 1 0 Switched to not addressed slave
mode; Own slave address will be
recognized; General Call will be
recognized if GC = 1. A START
condition will be transmitted when
the bus becomes free.
Table 31. Slave Receiver Byte mode (MODE = 0)
…continued
Status
code
(I2CSTA)
Status of the
I
2
C-bus and the
PCA9665
Application software response Next action taken by the
PCA9665
To/from I2CDAT To I2CCON
STA STO SI AA MODE
PCA9665_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 August 2008 29 of 90
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
8.3.4 Slave Transmitter Byte mode
In the Slave Transmitter Byte mode, a number of data bytes are transmitted to a master
receiver one byte at a time (see Figure 10). Data transfer is initialized as in the Slave
Receiver Byte mode. When I2CADR and I2CCON have been initialized, the PCA9665
waits until it is addressed by its own slave address followed by the data direction bit which
must be ‘1’ (R) for the PCA9665 to operate in the Slave Transmitter mode. After its own
slave address and the R bit have been received, the Serial Interrupt flag (SI) is set, the
Interrupt line (INT) goes LOW and I2CSTA is loaded with A8h. This status code is used to
vector to an interrupt service routine, and the appropriate action to be taken is detailed in
Table 32.
The Slave Transmitter Byte mode may also be entered if arbitration is lost while the
PCA9665 is in the master mode. See state B0h and appropriate actions in Table 32.
If the AA bit is reset during a transfer, the PCA9665 will transmit the last byte of the
transfer and enter state C8h. The PCA9665 is switched to the not addressed slave mode
and will ignore the master receiver if it continues the transfer. Thus the master receiver
receives all ‘1’s as serial data. While AA is reset, the PCA9665 does not respond to its
own slave address. However, the I
2
C-bus is still monitored, and address recognition may
be resumed at any time by setting AA. This means that the AA bit may be used to
temporarily isolate SIO from the I
2
C-bus.
(1) See Table 31.
(2) Defined state when a single byte is transmitted and an ACK is received.
(3) Defined state when a single byte is transmitted and a NACK is received.
(4) Defined state when a single byte is transmitted and the PCA9665 goes to the non-addressed mode (AA = 0) and an ACK is
received.
Fig 10. Format and states in the Slave Transmitter Byte mode (MODE = 0)
S SLA R A
DATA
A P or S
A8h
B8h F8h
002aab027
reception of own
slave address and
transmission of one
or more data bytes
arbitration lost as MST and
addressed as slave
n
This number (contained in I2CSTA) corresponds
to a defined state of the I
2
C-bus.
(1)
DATA
A
any number of data bytes and
their associated Acknowledge bits
from master to slave
from slave to master
DATA A
C0h
P or S
F8h
A
C8h
on STOP
on STOP
A
B0h
last data byte transmitted;
switched to Not Addressed slave
(AA bit in I2CCON = 0)
ALL '1's
(2) (3)
(4)
PCA9665_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 August 2008 30 of 90
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
Table 32. Slave Transmitter Byte mode (MODE = 0)
Status
code
(I2CSTA)
Status of the
I
2
C-bus and the
PCA9665
Application software response Next action taken by PCA9665
To/from I2CDAT To I2CCON
STA STO SI AA MODE
A8h Own SLA+R has
been received; ACK
has been returned
Load data byte
or
X X 0 0 0 Last data byte will be transmitted and
ACK/NACK bit will be received
load data byte X X 0 1 0 Data byte will be transmitted;
ACK/NACK will be received
B0h Arbitration lost in
SLA+R/W as
master; Own SLA+R
has been received,
ACK has been
returned
Load data byte
or
X X 0 0 0 Last data byte will be transmitted and
ACK/NACK bit will be received
load data byte X X 0 1 0 Data byte will be transmitted;
ACK bit will be received
B8h Data byte in I2CDAT
has been
transmitted; ACK
has been received
Load data byte
or
X X 0 0 0 Last data byte will be transmitted and
ACK/NACK bit will be received
load data byte X X 0 1 0 Data byte will be transmitted;
ACK/NACK bit will be received
C0h Data byte in I2CDAT
has been
transmitted; NACK
has been received
No I2CDAT
action or
0 X 0 0 0 Switched to not addressed slave mode;
no recognition of own slave address.
General Call address recognized if
GC=1.
no I2CDAT
action or
0 X 0 1 0 Switched to slave mode; Own slave
address will be recognized. General
Call address recognized if GC = 1.
no I2CDAT
action or
1 X 0 0 0 Switched to not addressed slave mode;
no recognition of own slave address.
General Call address recognized if
GC = 1. A START condition will be
transmitted when the bus becomes free
no I2CDAT
action
1 X 0 1 0 Switched to slave mode; Own slave
address will be recognized. General
Call address recognized if GC = 1. A
START condition will be transmitted
when the bus becomes free.
C8h Last data byte in
I2CDAT has been
transmitted (AA = 0);
ACK has been
received
No I2CDAT
action or
0 X 0 0 0 Switched to not addressed slave mode;
no recognition of own slave address.
General Call address recognized if
GC=1.
no I2CDAT
action or
0 X 0 1 0 Switched to slave mode; Own slave
address will be recognized. General
Call address recognized if GC = 1.
no I2CDAT
action or
1 X 0 0 0 Switched to not addressed slave mode;
no recognition of own slave address.
General Call address recognized if
GC = 1. A START condition will be
transmitted when the bus becomes free
no I2CDAT
action
1 X 0 1 0 Switched to slave mode; Own slave
address will be recognized. General
Call address recognized if GC = 1. A
START condition will be transmitted
when the bus becomes free.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84P85-P87P88-P90

PCA9665N,112

Mfr. #:
Buy PCA9665N,112
Manufacturer:
NXP Semiconductors
Description:
IC CNTRLR PARALLEL/I2C 20-DIP
Lifecycle:
New from this manufacturer.
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