PCA9665N,112 Datasheet PCA9665N,112 | P7-P9

Product data sheet Rev. 03 — 12 August 2008 7 of 90

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

Table 4. Indirect register selection by setting A1 = 1 and A0 = 0

I2CCOUNT byte count 00h R/W 01h

I2CADR own address 01h R/W E0h

I2CSCLL SCL LOW period 02h R/W 9Dh

I2CSCLH SCL HIGH period 03h R/W 86h

I2CTO time-out 04h R/W FFh

I2CPRESET parallel software reset 05h W 00h

I2CMODE I

C-bus mode 06h R/W 00h

Fig 6. Register mapping ﬂowchart

002aab459

I2CSTA REGISTER

A1 A0 = 00

read?

yes

INDPTR REGISTER

A1 A0 = 00

write?

yes

A1 A0 = 10

read/write?

yes

INDPTR = 00h

yes

I2CCOUNT REGISTER

A1 A0 = 01

read/write?

INDPTR = 01h

yes

I2CADR REGISTER

I2CDAT REGISTER

yes

A1 A0 = 11

read/write?

INDPTR = 02h

yes

I2CSCLL REGISTER

I2CCON REGISTER

yes

INDPTR = 03h

yes

I2CSCLH REGISTER

INDPTR = 04h

yes

I2CTO REGISTER

INDPTR = 05h

yes

I2CPRESET REGISTER

INDPTR = 06h

yes

I2CMODE REGISTER

RESERVED

(write only)

Product data sheet Rev. 03 — 12 August 2008 8 of 90

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

7.3.1 Direct registers

7.3.1.1 The Status register, I2CSTA (A1 = 0, A0 = 0)

I2CSTA is an 8-bit read-only register. The two least signiﬁcant bits are always zero. The

six most signiﬁcant bits contain the status code. There are 30 possible status codes.

When I2CSTA contains F8h, it indicates the idle state and therefore no serial interrupt is

requested. All other I2CSTA values correspond to deﬁned states. When each of these

states is entered, a serial interrupt is requested (SI = 1 and INT asserted LOW).

Remark: Data in I2CSTA is valid only when a serial interrupt occurs (SI = 1 and INT

asserted LOW). Reading the register when SI = 0 and INT is HIGH may cause wrong

values to be read.

7.3.1.2 The Indirect Pointer register, INDPTR (A1 = 0, A0 = 0)

INDPTR is an 8-bit write-only register. It contains a pointer to a register in the indirect

address space (IP[2:0]). The value in the register will determine what indirect register will

be accessed when the INDIRECT register is read or written, as deﬁned in Table 4.

7.3.1.3 The I

C-bus Data register, I2CDAT (A1 = 0, A0 = 1)

I2CDAT is an 8-bit read/write register. It contains a byte of serial data to be transmitted or

a byte which has just been received. In master mode, this includes the slave address that

the master wants to send out on the I

C-bus, with the most signiﬁcant bit of the slave

address in the SD7 bit position and the Read/Write bit in the SD0 bit position. The CPU

can read from and write to this 8-bit register while the PCA9665 is not in the process of

shifting a byte. This occurs when PCA9665 is in a deﬁned state and the serial interrupt

ﬂag is set. Data in I2CDAT remains stable as long as SI is set. Whenever the PCA9665

generates an interrupt, the I2CDAT register contains the data byte that was just

transferred on the I

C-bus.

Table 5. I2CSTA - Status register (A1 = 0, A0 = 0) bit allocation

7 6 5 4 3 2 1 0

ST5 ST4 ST3 ST2 ST1 ST0 0 0

Table 6. I2CSTA - Status register (A1 = 0, A0 = 0) bit description

Bit Symbol Description

7:2 ST[5:0] status code corresponding to the different I

C-bus states

1:0 - always at zero

Table 7. INDPTR - Indirect Register Pointer (A1 = 0, A0 = 0) bit allocation

7 6 5 4 3 2 1 0

- - - - - IP2 IP1 IP0

Table 8. INDPTR - Indirect Pointer register (A1 = 0, A0 = 0) bit description

Bit Symbol Description

7:3 - reserved; must be written with zeroes

2:0 IP2 to IP0 address of the indirect register

Product data sheet Rev. 03 — 12 August 2008 9 of 90

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

In Byte mode, the CPU can read or write a single byte at a time. In Buffered mode, the

CPU can read or write up to 68 bytes at a time. See Section 8.1 “Conﬁguration modes” for

more detail.

Remark: The I2CDAT register will capture the serial address as data when addressed via

the serial bus.

Remark: In Byte mode only, the data register will capture data from the serial bus during

38h (arbitration lost in slave address + R/W or data bytes causing this data in I2CDAT to

be changed), so the I2CDAT register will need to be reloaded when the bus becomes free.

In Buffered mode, the data is not written in the data register when arbitration is lost, which

keeps the buffer intact.

7.3.1.4 The Control register, I2CCON (A1 = 1, A0 = 1)

I2CCON is an 8-bit read/write register. Two bits are affected by the bus controller

hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared

when a STOP condition is present on the I

C-bus. A Write to the I2CCON register via the

parallel interface automatically clears the SI bit, which causes the Serial Interrupt line to

be de-asserted and the next clock pulse on the SCL line to be generated.

Remark: Since none of the registers should be written to via the parallel interface once

the Serial Interrupt line has been de-asserted, all the other registers that need to be

modiﬁed should be written to before the content of the I2CCON register is modiﬁed.

Table 9. I2CDAT - Data register (A1 = 0, A0 = 1) bit allocation

7 6 5 4 3 2 1 0

SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

Table 10. I2CDAT - Data register (A1 = 0, A0 = 1) bit description

Bit Symbol Description

7:0 SD[7:0] Eight bits to be transmitted or just received. A logic 1 in I2CDAT corresponds to

a HIGH level on the I

C-bus. A logic 0 corresponds to a LOW level on the bus.

Table 11. I2CCON - Control register (A1 = 1, A0 = 1) bit allocation

7 6 5 4 3 2 1 0

AA ENSIO STA STO SI - - MODE

PCA9665N,112

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