PCA9665N,112 Datasheet PCA9665N,112 | P16-P18

Product data sheet Rev. 03 — 12 August 2008 16 of 90

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

8. PCA9665 modes

8.1 Conﬁguration modes

Byte mode and Buffered mode are selected using the MODE bit in I2CCON register:

MODE = 0: Byte mode

MODE = 1: Buffered mode

8.1.1 Byte mode

The Byte mode allows communication on a single command basis. Only one speciﬁc

command is executed at a time and the Status Register is updated once this single

command has been performed. A command can be a START, a STOP, a Byte Write, a

Byte Read, and so on.

8.1.2 Buffered mode

The Buffered mode allows several instructions to be executed before an Interrupt is

generated and before the I2CSTA register is updated. This allows the microcontroller to

request a sequence, up to 68 bytes in a single transmission and lets the PCA9665

perform it without having to access the Status Register and the Control Register each time

a single command is performed. The microcontroller can then perform other tasks while

the PCA9665 performs the requested sequence.

The number of bytes that needs to be sent from the internal buffer (Transmitter mode) or

received into the internal buffer (Receiver mode) is deﬁned in the indirectly addressed

I2CCOUNT Register (BC[6:0]). Up to 68 bytes can be sent or received.

8.2 Operating modes

The four operating modes are:

• Master Transmitter

• Master Receiver

• Slave Receiver

• Slave Transmitter

Each mode can be used on a byte basis (Byte mode) or in an up to 68-byte buffer basis

(Buffered mode).

Data transfers in each mode of operation are shown in Figure 7 through Figure 10. These

ﬁgures contain the following abbreviations:

S — START condition

SLA — 7-bit slave address

R — Read bit (HIGH level at SDA)

W — Write bit (LOW level at SDA)

A — Acknowledge bit (LOW level at SDA)

A — Not acknowledge bit (HIGH level at SDA)

Data — 8-bit data byte

Product data sheet Rev. 03 — 12 August 2008 17 of 90

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

P — STOP condition

In Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13 and Figure 14,

circles are used to indicate when the serial interrupt ﬂag is set. A serial interrupt is not

generated when I2CSTA = F8h. This happens on a STOP condition or when an external

reset is generated (at power-up, when RESET pin is going LOW or during a software reset

on the parallel bus). The numbers in the circles show the status code held in the I2CSTA

serial transfer. These service routines are not critical since the serial transfer is

suspended until the serial interrupt ﬂag is cleared by software.

When a serial interrupt routine is entered, the status code in I2CSTA is used to branch to

the appropriate service routine. For each status code, the required software action and

details of the following serial transfer are given in Table 27, Table 28, Table 31, Table 32,

Table 35, Table 36, Table 40, and Table 41.

8.3 Byte mode

8.3.1 Master Transmitter Byte mode

In the Master Transmitter Byte mode, a number of data bytes are transmitted to a slave

receiver (see Figure 7). Before the Master Transmitter Byte mode can be entered,

I2CCON must be initialized as shown in Table 26.

ENSIO must be set to logic 1 to enable the PCA9665. If the AA bit is reset, the PCA9665

will not acknowledge its own slave address in the event of another device becoming

master of the bus. (In other words, if AA is reset, PCA9665 cannot enter a slave mode.)

STA, STO, and SI must be reset. Once ENSIO has been set to 1, it takes about 550 µsfor

the oscillator to start up.

The Master Transmitter Byte mode may now be entered by setting the STA bit. The

C-bus state machine will ﬁrst test the I

C-bus and generate a START condition as soon

as the bus becomes free. When a START condition is transmitted, the serial interrupt ﬂag

(SI) is set, the Interrupt line (INT) goes LOW and the status code in the status register

(I2CSTA) will be 08h. This status code must be used to vector to an interrupt service

routine that loads I2CDAT with the slave address and the data direction bit (SLA+W). A

write to I2CCON resets the SI bit, clears the Interrupt (INT goes HIGH) and allows the

serial transfer to continue.

When the slave address with the direction bit have been transmitted, the Serial Interrupt

ﬂag (SI) is set again, the Interrupt line (INT) goes LOW again and I2CSTA is loaded with

the following possible codes:

• 18h if an acknowledgment bit (ACK) has been received

• 20h if an no acknowledgment bit (NACK) has been received

• 38h if the PCA9665 lost the arbitration

Table 26. I2CCON initialization (Byte mode)

Bit 7 6 5 4 3 2 1 0

Symbol AA ENSIO STA STO SI reserved reserved MODE

Value X1000XX0

Product data sheet Rev. 03 — 12 August 2008 18 of 90

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

• B0h if the PCA9665 lost the arbitration and is addressed as a slave transmitter (slave

mode enabled with AA = 1)

• 68h if the PCA9665 lost the arbitration and is addressed as a slave receiver (slave

mode enabled with AA = 1)

• D8h if the PCA9665 lost the arbitration and is addressed as a slave receiver during a

General Call sequence (slave mode enabled with AA = 1 and General Call address

enabled with GC = 1 in I2CADR register)

The appropriate action to be taken for each of these status codes is detailed in Table 27.

ENSIO is not affected by the serial transfer and is not referred to in Table 27.

After a repeated START condition (state 10h), the PCA9665 may switch to the Master

Receiver mode by loading I2CDAT with SLA+R.

Remark: A master should not transmit its own slave address.

PCA9665N,112

Mfr. #:

Buy PCA9665N,112

Manufacturer:

NXP Semiconductors

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IC CNTRLR PARALLEL/I2C 20-DIP

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