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SC28L202A1DGG,129

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P77
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
7
interrupt parameters and for writing to and reading from FIFOs
without explicitly addressing them.
The CIR will load with 0x00 if IACKN or Update CIR is asserted
when the arbitration circuit is NOT asserting an interrupt. In this
condition there is no arbitration value that exceeds the threshold
value. When Interrupt vector modification is active in this situation
the interrupt vector bits associated with the CIR will all be zero. A
zero type field indicates nothing with in the DUART is requiring
processor service.
NOTE: IACKN is essentially a special read action where the value of
the interrupt vector is presented to the data bus.
Timing Circuit
Crystal Oscillator
The crystal oscillator operates directly from a crystal, tuned between
7.0 MHz and 16.2 MHz connected across the X1/Sclk and X2 inputs
with a minimum of external components. BRG values listed for the
clock select registers correspond to a 14.7456 MHz crystal
frequency. Use of different frequencies will change the ‘standard’
baud rates by precisely the ratio of 14.7456 MHz to the different
crystal frequency.
An external clock up to 50 MHz frequency range may be connected
to X1/Sclk pin. If an external clock is used instead of a crystal,
X1/Sclk must be driven and X2 left floating or driving a load of not
more than 2 CMOS or TTL equivalents. The X1/Sclk clock serves as
the basic timing reference for the baud rate generator (BRG) and is
available to the programmable BRG (PBRG), counter-timers, control
logic and the UART receivers and transmitters.
Baud Rate Generator BRG
The baud rate generator operates from the oscillator or external
X1/Sclk clock input and generates 27 commonly used data
communications baud rates (including MIDI) ranging from 50 baud
to 921.6K baud. These common rates may be increased (up to
3000K baud) when faster clocks are used on the X1/Sclk clock
input. (See Receiver and Transmitter Clock Select Register
descriptions.) All of these are available simultaneously for use by
any receiver or transmitter. The clock outputs from the BRG are at
16X the actual baud rate.
Please see counter timer description for a description of the
frequency error that the asynchronous protocol may tolerate.
Depending on character length it varies from 4.1% to 6.7%.
Counter-Timer
The two Counter/Timers are programmable 16 bit dividers that are
used for generating miscellaneous clocks or generating timeout
periods or counting characters received by the receivers. Interrupts
may be generated any time the counter passes through 0x00. These
clocks may be used by any or all of the receivers and transmitters in
the DUART or may be directed to an I/O pin for miscellaneous use.
Counter/Timer programming
The counter timer is a 16-bit programmable divider that operates in
one of four modes: character count, counter, timer, and time out.
Character count counts characters. The timer mode generates a
square wave. In the counter mode it generates a time delay. In the
time out mode it monitors the time between received characters.
The C/T uses the numbers loaded into the Counter/Timer Lower
Register (CTPL) and the Counter/Timer Upper Register (CTPU) as
its divisor. The counter timer is controlled with six commands:
Start/Stop C/T, Read/Write Counter/Timer lower register and
Read/Write Counter/Timer upper register. These commands have
slight differences depending on the mode of operation. Please see
the detail of the commands under the CTPL/CTPU Register
descriptions.
Whenever the these timers are selected via the receiver or
transmitter Clock Select register their output will be configured as a
16x clock for the respective receiver or transmitter. Therefore one
needs to program the timers to generate a clock 16 times faster than
the data rate. The formula for calculating ’n’, the number loaded to
the CTPU and CTPL registers, based on a particular input clock
frequency is shown below.
For the timer mode the formula is as follows:
n +
C/T clock input frequency
(2 16 (desired baud rate))
(If the pulse mode is selected, then ‘2’ in the divisor should be ‘1’.
This doubles the C/T output speeds for any given input clock.)
NOTE: ‘n’ may assume a value of 1. In previous Philips data
communications controllers this value was not allowed. The
Counter/Timer Clock Select Register (CTCS) controls the
Counter/Timer input frequency.
The frequency generated from the above formula will be at a rate 16
times faster than the desired baud rate. The transmitter and receiver
state machines include divide by 16 circuits, which provide the final
frequency and provide various timing edges used in the qualifying
the serial data bit stream. Often this division will result in a
non-integer value: 26.3 for example. One may only program integer
numbers to a digital divider. There for 26 would be chosen. If 26.7
were the result of the division then 27 would be chosen. This gives a
baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage error
of 1.14% or 1.12% respectively, well within the ability of the
asynchronous mode of operation. Higher input frequency to the
counter reduces the error effect of the fractional division.
One should be cautious about the assumed benign effects of small
errors since the other receiver or transmitter with which one is
communicating may also have a small error in the precise baud rate.
In a ‘clean’ communications environment using one start bit, eight
data bits and one stop bit the total difference allowed between the
transmitter and receiver frequency is approximately 4.6%. Less than
eight data bits will increase this percentage.
Programmable Baud Rate Generators. PBRG
Two PBRG Counters (Used only for random baud rate generation)
The two PBRG Timers are programmable 16 bit dividers that are
used for generating miscellaneous clocks. These clocks may be
used by any or all of the receivers and transmitters in the SC28L202
or output to the general purpose I/O pins.
Each timer unit has eight different clock sources available to it as
described in the PBRG clock source Register. Note that the timer
run and stop controls are also contained in this register. The PBRG
counters generate a symmetrical square wave whose half period is
equal in time to the division of the selected PBRG Timer clock
source by the number loaded to the PBRGPU and PBRGPL Preset
Registers. Thus, the output frequency will be the clock source
frequency divided by twice the 16 bit value loaded to these registers.
This is the result of counting down once for the high portion of the
output wave and once for the low portion.
Whenever the these timers are selected via the receiver or
transmitter Clock Select register their output will be configured as a
16x clock for the respective receiver or transmitter. Therefore one
needs to program the timers to generate a clock 16 times faster than
the data rate. The formula for calculating ’n’, the number loaded to
the PBRGPL and PBRGPU registers, is the same as shown above.
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
8
I/O Ports
Eight I/O ports are ‘loosely’ provided for each channel. They may be
programmed to be inputs or outputs. The input circuits are always
active whether programmed as and input or an output. In general a
2-bit code in the
I/OPCR
(I/O Port Control Register) controls what
function these pins will present. All I/O ports default to high
impedance input state on power up. All 16 I/O pins have a small
pull-up ‘resistor’ that provides approximately 5 µA current.
When calling software written for legacy two channel UARTs
manufactured by Philips (Signetics), be sure I/O pins are set to
input where the legacy software expected an input. Declare I/O
pins as output where the legacy software expected an output.
Input Characteristics of the I/O ports
Eight I/O pins are provided for each channel. These pins are
configured individually to be inputs or outputs. As inputs they may
be used to bring external data to the bus, as clocks for internal
functions or external control signals. Each I/O pin has a ‘Change of
State’ detector. The change detectors are used to signal a change in
the signal level at the pin (Either 0-to-1 or 1-to-0 transitions). The
level change on these pins must be stable for 25 to 50 µs (two
edges of the internally generated 38.4 kHz baud rate clock) before
the detectors will signal a valid change. These are typically used for
interface signals from modems to the DUART and from there to the
host.
Output Port of the I/O ports
The OPR, I/OPCR, MR, and CR registers may control the I/O pins
when configured as outputs. (For the control in the lower 16 position
address space the control register is the OPCR) Via appropriate
programming the pins of the output port may be configures as
another parallel port to external circuits, or they may represent
internal conditions of the UART. When this 8-bit port is used as a
general-purpose output port, the output port pins drive inverse logic
levels of the individual bits in the Output Port Register (OPR). The
OPR register is set and reset by writing to the SOPR and ROPR
addresses. (See the description of the SOPR and ROPR registers).
The output pins will drive the same data polarity of the OPR
registers. The I/OPCR (or the OPCR) register conditions these
output pins to be controlled by the OPR or by other signals in the
chip. Output ports are driven high on hardware reset.
UART Operation
Receiver and Transmitter
The Dual UART has two full duplex asynchronous
receiver/transmitters. The operating frequency for the receiver and
transmitter can be selected independently from the baud rate
generator, the counter, or from an external input. Registers that are
central to basic full-duplex operation are the mode registers (MR0,
MR1 and MR2), the clock select registers (RxCSR and TxCSR), the
command register (CR), the status register (SR), the transmit
holding register (TxFIFO), the receive holding register (RxFIFO),
interrupt status register (ISR) and interrupt mask register (IMR).
MR3 controls the automatic activity or the Xon/Xoff flow control,
Address recognition, multi-drop (‘9-bit’ mode) and general purpose
character recognition. Because MR3 does not exist in legacy
UARTs, these features should be disabled before legacy code is
loaded.
Transmitter Status Bits
The SR (Status Register, one per UART) contains two bits that show
the condition of the transmitter FIFO. These bits are TxRDY and Tx
Idle. TxRDY means the TxFIFO has space available for one or more
bytes; Tx Idle means The TxFIFO is completely empty and the last
stop bit has been completed—the transmitter is underrun. Tx Idle
can not be active without TxRDY also being active. These two bits
will go active upon initial enabling of the transmitter.
The transmitter status bits are normally cleared by servicing the
interrupt condition they represent or by Tx reset or Tx disable
commands.
Transmission resumes and the Tx Idle bit is cleared when the CPU
loads at least one new character into the TxFIFO. The TxRDY will
not extinguish until the TxFIFO is completely full. The TxRDY bit will
always be active when the transmitter is enabled and there is at
lease one open position in the TxFIFO.
The transmitter is disabled by a hardware reset, a transmitter reset
in the command register or by the transmitter disable bit also in the
command register (CR). The transmitter must be explicitly enabled
via the CR before transmission can begin. Note that characters
cannot be loaded into the TxFIFO while the transmitter is disabled,
hence it is necessary to enable the transmitter and then load the
TxFIFO. It is not possible to load the TxFIFO and then enable the
transmission.
Note the difference between transmitter disable and transmitter
reset.
Either hardware or software may cause the reset action. When reset
the transmitter stops transmission immediately. The transmit data
output will be driven high, transmitter status bits set to zero and any
data remaining in the TxFIFO is effectively discarded.
The transmitter disable is controlled by the Tx Enable bit in the
command register. Setting this bit to zero will not stop the transmitter
immediately but will allow it to complete any tasks presently
underway. It is only when the last character in the TxFIFO and its
stop bit(s) have been transmitted that the transmitter will go to its
disabled state. While the transmitter enable/disable bit in the
command register is at zero the TxFIFO will not accept any more
characters and the Tx Idle and TxRDY bits of the status register set
to zero.
Transmission of ‘break’
Transmission of a break character is often needed as a
synchronizing condition in a data stream. The ‘break’ is defined as a
start bit followed by all zero data bits by a zero parity bit (if parity is
enabled) and a zero in the stop bit position. The forgoing is the
minimum time to define a break. The transmitter can be forced to
send a break (continuous low condition) by issuing a start break
command via the CR. Once the break starts, the TxD output
remains low until the host issues a command to ‘stop break’ via the
CR or the transmitter is issued a software or hardware reset. In
normal operation the break is usually much longer than one
character time.
1x and 16x modes, Transmitter
The transmitter clocking has two modes: 16x and 1x. Data is always
sent at the 1x rate. However the logic of the transmitter may be
operated with a clock that is 16 times faster than the data rate or at
the same rate as the data i.e. 1x. All clocks selected internally for
the transmitter (and the receiver) will be 16x clocks. Only when an
external clock is selected may the transmitter logic and state
machine operate in the 1x mode. The 1x or 16x clocking makes little
difference in transmitter operation. (This is not true in the receiver)
In the 16X-clock mode the transmitter will recognize a byte in the
TxFIFO within 1/16 to 2/16-bit time and thus begin transmission of
the start bit. In the 1x mode this delay may be up to 2 bit times.
Transmitter FIFO
The FIFO configuration of the as 28L202 is 256 8-bit words.
Interrupt levels may be set to any level within the FIFO size and may
be set differently for each FIFO. Logic associated with the FIFO
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
9
encodes the number of empty positions for presentation to the
interrupt arbitration system. The encoding value is the number of
empty positions. Thus, an empty TxFIFO will bid with the value or
255; when full it will not bid at all; one position empty bids with the
value 0. A Full TxFIFO will not bid since no character is available.
Normally TxFIFO will present a bid to the arbitration system
whenever it has one or more empty positions. The Bits of the
TxFIFO Interrupt Level in the MR0(5:4) allow the user to modify this
characteristic so that bidding will not start until one of four levels
(one or more filled, empty, 16 filled, 240 filled, full) have been
reached. As will be shown later this feature may be used to make
moderate improvements in the interrupt service efficiency. A similar
system exists for the Receiver.
Transmitter
The 28L202 is conditioned to transmit data when the transmitter is
enabled through the command register. The transmitter of the
28L202 indicates to the CPU that it is ready to accept a character by
setting the ISR TxRDY bit in the status register. This condition can
be programmed to generate an interrupt request at
I/O4
or IRQN.
When the transmitter is initially enabled the TxRDY and Tx Idle bits
will be set in the status register. When a character is loaded to the
transmit FIFO the Tx Idle bit will be reset. The Tx Idle bit will not set
until the transmit FIFO is empty and the transmit shift register has
finished transmitting the stop bit of the last character written to the
transmit FIFO.
The TxRDY bit is set whenever the transmitter is enabled and the
TxFIFO is not full. Data is transferred from the holding register to
transmit shift register when it is idle or has completed transmission
of the previous character. Characters cannot be loaded into the
TxFIFO while the transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the TxFIFO, the TxD output remains
High and the Tx Idle bit in the Status Register (SR) will be set to 1.
Transmission resumes and the Tx Idle bit is cleared when the CPU
loads a new character into the TxFIFO.
If the transmitter is disabled, it continues operating until the
character currently being transmitted is completely sent out. The
transmitter can be forced to send a continuous Low condition by
issuing a send break command. The transmitter can be reset
through a software command. If it is reset, operation ceases
immediately and the transmitter must be enabled through the
command register before resuming operation.
If CTS option of hardware flow control is enabled (MR2 [4] = 1), the
CTS input at I/O0 or I/O1 must be Low in order for the character to
be transmitted. The transmitter will check the state of the CTS input
at the beginning of each character transmitted. If it is found to be
High, the transmitter will delay the transmission of any following
characters until the CTS has returned to the low state. CTS going
high during the serialization of a character will not affect that
character.
It is an interesting point of the I/O system inputs being always active
that by enabling transmitter to be sensitive the I/O0 or I/O1 and then
controlling the I/O pin as an out put that one is able to control the
transmitter flow via software control of the I/O pin.
The transmitter can also control the RTSN outputs, I/O0 or I/O1 via
MR2 [5]. When this mode of operation is set (often referred to as the
RS-485 method) the meaning of the I/O0 B or I/O1 B signals is ‘all
bytes loaded to the transmitter’s FIFO have been transmitted
including the last stop bit(s). See the MR2(5) description for enabling
this automatic function.
Receiver Operation
Receiver
The receiver accepts serial data on the RxD pin, converts the serial
input to parallel format, checks for start bit, stop bit, parity bit (if any),
framing error or break condition, and presents the assembled
character and its status condition to the CPU via the RxFIFO. Three
status bits are FIFOed with each character received. The RxFIFO is
really 11 bits wide: eight data and 3 status. Unused FIFO bits for
character lengths less than 8 bits are set to zero.
It is important to note that in the asynchronous protocol the receiver
logic considers the entire message to be contained within the start
bit to the stop bit. It is not aware that a message may contain many
characters. The receiver returns to its idle mode at the end of each
stop bit! As described below it immediately begins to search for
another start bit, which is normally, of course, immediately
forthcoming.
1x and 16x mode, Receiver
The receiver operates in one of two modes: 1x and 16x. Of the two,
the 16x is more robust and the preferred mode. Although the 1x
mode may allow a faster data rate is does not provide for the
alignment of the receiver 1x data clock to that of the transmitter. This
strongly implies that the 1x clock of the remote transmitter is
available to the receiver; the two devices are physically close to
each other.
The 16x mode operates the receiver logic at a rate 16 times faster
than the 1x data rate. This allows for validation of the start bit length,
the validation of level changes at the receiver serial data input
(RxD), and the validation of the stop bit length. Of most importance
in the 16x mode is the ability of the receiver logic to align the phase
of the internally generated receiver 1x data clock to that of the
received start bit of the remote transmitter. This occurs with an
accuracy of less than 1/16 bit time.
Receiver
The receiver of the 28L202 is conditioned to receive data when
enabled through the command register. The receiver looks for a
High-to-Low (mark-to-space) transition of the start bit on the RxD
input pin. If a transition is detected, the state of the RxD pin is
sampled each 16X clock for 7-1/2 clock periods (16X clock mode) or
at the next rising edge of the bit time clock (1X clock mode). If RxD
is sampled high, (that is the start bit was low less than 7/16 to ½ bit
time) the start bit is judged invalid and the search for another valid
start bit begins immediately. If RxD is still low, a valid start bit is
assumed and the receiver then continues to sample the input at
one-bit time intervals at the theoretical center of the bit. When the
proper number of data bits and parity bit (if used) have been
assembled, and one half-stop bit has been detected the receiver
loads the byte to the FIFO. The least significant bit is received first.
The data is then transferred to the Receive FIFO and the ISR
RxRDY bit in the SR is set to a 1. This condition can be
programmed to generate an interrupt at IRQN or I/O[4:5] for
channels A or B respectively. If the character length is less than 8
bits, the most significant unused bits in the RxFIFO are set to zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received with
the stop bit at a zero level (framing error) and RxD remains Low for
at least another one half bit time after the stop bit was sampled, then
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P77

SC28L202A1DGG,129

Mfr. #:
Buy SC28L202A1DGG,129
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 3-5V 2CH UART 3MBPS
Lifecycle:
New from this manufacturer.
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