SC28L202A1DGG,129 Datasheet SC28L202A1DGG,118, SC28L202A1DGG,112, SC28L202A1DGG,129 | P16-P18

Philips Semiconductors Product data sheet

SC28L202Dual UART

2005 Nov 01

the receiver operates as if a new start bit had been detected. It then

continues assembling the next character.

The error conditions of parity error, framing error, and overrun error

(if any) are written to the SR at the received character boundary.

This is just before the RxRDY status bit is set.

A break condition is detected when RxD is Low for the entire

character including the parity bit, if used, and stop bit. When a break

is found a character consisting of all zeros will be loaded into the

RxFIFO, the received break bit in the SR and the ‘change of break’

bit in the ISR are set to 1 and the receiver ready is set in the SR.

The RxD input must

return to high for two (2) clock edges

of the

RxC1x clock for the receiver to recognize the end of the break

condition. At the end of the break condition the search for the next

start bit begins.

Two edges of the RxC1x clock will usually require a high time of one

RxC1x clock period or 3 RxC1x edges since the clock of the

controller is usually not synchronous to nor in phase with the RxC1x

clock.

Receiver Status Bits

There are five (5) status bits that are evaluated with each byte (or

character) received: received break, framing error, parity error,

overrun error, and change of break. The first three are appended to

each byte and stored in the RxFIFO. The last two are not

necessarily related to the byte being received or a byte that is in the

RxFIFO. They are however developed by the receiver state

machine.

The receiver status bits are normally cleared by servicing the

interrupt condition they represent or by Rx reset or Rx disable

commands or the several error reset commands in the Command

The ‘received break’ will always be associated with a zero byte in

the RxFIFO. It means that zero character was a break character and

not a zero data byte. The reception of a break condition will always

set the ‘change of break’ (see below) status bit in the Interrupt

Status Register (ISR).

The Change of break condition is reset by a reset error status

command in the command register

A framing error occurs when a non-zero character was seen and

that character has a zero in the stop bit position.

The parity error indicates that the receiver-generated parity was not

the same as that sent by the transmitter.

The framing, parity and received break status bits are reset when

the associated data byte is read from the RxFIFO since these ‘error’

conditions are attached to the byte that has the error

The overrun error occurs when the RxFIFO is full, the receiver shift

receiver has 257 valid characters and the start bit of the 258

has

been seen. At this point the host has approximately 6/16 bit time to

read a byte from the RxFIFO or the overrun condition will be set.

The 258

character then overruns the 257

and the 258

the 259

and so on until an open position in the RxFIFO is seen. (‘seen’

meaning at least one byte was read from the RxFIFO.)

Overrun is cleared by a use of the ‘error reset’ command in the

command register.

The fundamental meaning of the overrun is that data has been lost.

Data in the RxFIFO remains valid. The receiver will begin placing

characters in the RxFIFO as soon as a position becomes vacant.

NOTE: Precaution must be taken when reading an overrun FIFO.

There will be 256

valid characters in the receiver FIFO. There will

be one character in the receiver shift register. However it will NOT

be known if more than one ‘over-running’ character has been

received since the overrun bit was set. The 257

character received

and read as valid but it will not be known how many characters were

lost between the two characters of the 256

and 257

reads of the

RxFIFO. In the 8-bit mode, the numbers 8 and 9 replace the

numbers 256 and 257 above.

The ‘Change of break’ means that either a break has been detected

or that the break condition has been cleared. This bit is available in

the ISR. The break change bit being set in the ISR and the received

break bit being set in the SR will signal the beginning of a break. At

the termination of the break condition only the change of break in

the ISR will be set. After the break condition is detected the

termination of the break will only be recognized when the RxD input

has returned to the high state for two successive edges of the 1x

clock; 1/2 to 1 bit time. (see above)

The receiver is disabled by reset or via CR commands. A disabled

receiver will not interrupt the host CPU under any circumstance in

the normal mode of operation. If the receiver is in the multi-drop or

special mode, it will be partially enabled and thus may cause an

interrupt. Refer to section on Wake-Up and the register description

for MR1 for more information.

Receiver FIFO

The receiver buffer memory is a 256 byte FIFO with three status bits

appended to each data byte. (The FIFO is then 256 11-bit ‘words’).

The receiver state machine gathers the bits from the receiver shift

assembled byte and status bits to the RxFIFO shortly after the stop

bit has been sampled. Logic associated with the FIFO encodes the

number of filled positions for presentation to the interrupt arbitration

system. The encoding is always the number of filled positions. Thus,

a full RxFIFO will bid with the value of 255 and the Status Register

RxFULL bit is set. When empty it will not bit at all. One position

occupied bids with the value 1. An empty FIFO will not bid since no

character is available.

Normally RxFIFO will present a bid to the arbitration system

whenever it has one or more filled positions. The bits of the RxFIFO

Interrupt Offset Level (RxFIL) or the bits of the MR2(3:2) allow the

user to modify this characteristic so that bidding will not start until

one of four levels (one or more filled, 64 filled, 192 filled, full) have

been reached. As will be shown later this feature may be used to

make slight improvements in the interrupt service efficiency. A

similar system exists in the transmitter.

RxFIFO Status Bits. Status reporting modes

This description applies to the upper three bits in the ‘Status

part of the RxFIFO. The three status bits at the output of the RxFIFO

are presented as the upper three bits of the status register included

in each UART.

The error status of a character, as reported by a read of the SR

(status register upper three bits) can be provided in two ways, as

programmed by the error mode control bit in the mode register:

‘Character mode’ or the ‘Block Mode’. The block mode may be

further modified (via a CR command) to set the status bits as the

characters enter the FIFO or as they are read from the FIFO.

In the ‘character’ mode, status is provided on a character by

character basis as the characters are read from the RxFIFO: the

‘status’ applies only to the character at the output of the

RxFIFO—The next character to be read.

Philips Semiconductors Product data sheet

SC28L202Dual UART

2005 Nov 01

In the ‘block’ mode (on entry) the status provided in the SR for these

three bits is the logical OR of the status for all characters coming to

the input of the RxFIFO since the last reset error command was

issued. In this mode each of the status bits stored in the RxFIFO are

passed through a latch as they are sequentially written to the

receiver FIFO. If any of the characters has an error bit set that latch

will set and remain set until it is reset with a ‘receiver reset’ issued

from the command register or a chip reset is issued. The purpose of

this mode is indicating an error in the data block as opposed to an

error in a character. This mode improves receiver service efficiency.

In modern systems with low error rates, it is more efficient to ask for

retransmit of a block error data than to analyze it on a byte by byte

system.

The above paragraph describes the block mode activity as the data

is entered to the RxFIFO. Normally the status would be read only

once—at the beginning of the service to the receiver interrupt. If an

error is not set then the entire amount of data in the RxFIFO would

be read without any more reading if the receiver status. This

effectively doubles the efficiency of reading the receiver RxFIFO.

The use of the block mode on Exit passes the data and error

conditions as the RxFIFO is read. Here the final read of the status

delays the knowledge of an error condition until after the data has

been read.

The latch used in the block mode to indicate ‘problem data’ is

usually set as the characters are read out of the RxFIFO. Via a

command in the CR the latch may be configured to set as error

characters are loaded to the RxFIFO. This gives the advantage of

indicating ‘problem data’ up to 256 (or the FIFO size) characters

earlier.

In either mode, reading the SR does not affect the RxFIFO. The

RxFIFO address is advanced only when the RxFIFO is read.

Therefore, the SR should be read prior to reading the corresponding

data character.

If the RxFIFO is full when a new character is received, the character

is held in the receiver shift register until a position is available in the

RxFIFO. At this time there are 257 valid characters in the RxFIFO. If

an additional character is received while this state exists, the

contents of the RxFIFO are not affected: the character previously in

the shift register is lost and the overrun error status bit, SR [4], will

be set upon receipt of the start bit of the new (overrunning)

character.

Wake Up Mode (Also the ‘9-bit’, ‘multi-drop’, ‘party; line’ or Special

mode)

The SC28L202 provides four modes of this common asynchronous

‘party line’ protocol where the parity bit is used to indicate that a byte

is address data or information data. Three automatic modes and the

default Host operated mode are provided. The automatic mode has

several sub modes (see below). In the full automatic the internal

state machine devoted to this function will handle all operations

associated with address recognition, data handling, receiver enables

and disables. In both modes the meaning of the parity bit is

changed. It is often referred to as the A/D bit or the address/data

bit—sometimes the ‘9th’ bit. It is used to indicate whether the byte

presently in the receiver shift register is an ‘address’ byte or a ‘data’

byte. A ‘1’ usually means address, a ‘0’ data.

Its purpose is to allow several receivers connected to the same data

source to be individually addressed. Of course addressing could be

by group also. Normally the ‘Master’ would send an address byte to

all receivers ‘listening’. The remote receiver will be ‘looking’ at the

data stream for its address. Upon recognition of its address it will

enable itself to receive the following data stream. Upon receipt of an

address not its own it would then disable itself. As descried below

appropriate status bits are available to describe the operation.

Again, for this mode an ‘address byte’ is a byte that has the bit in the

parity position set to logical 1.

The use of the multi-drop mode usually implies a ‘master and slave’

configuration of the several UART stations so programmed. The

software control should allow time for the slave stations to respond

to the receipt of an address bit. Often a reply from the addressed

station is expected to confirm the receipt of the address. Please see

control the automatic features of the address recognition in

MR3[1:0].

Enabling the Wake Up mode

(This mode is variously referred to as ‘9-bit’ or ‘Multi-drop’.)

This mode is selected by programming bits MR1 [4:3] (the parity

bits) to ’11’. The wake up feature has four modes of operation: one

strictly under processor control and three automatic. These modes

are controlled by bits 6, 1, 0 in the MR3 register. Bit 6 controls the

loading of the address byte to the RxFIFO and MR3[1:0] determines

the sub mode as shown in the following list.

MR3[1:0] = 00 Normal Wake Up Mode (default) which is the same

as previous DUARTs and is therefore controlled by the processor.

The Host controls operation via interrupts it receives and commands

it writes to the DUART command registers (CR).

Normal Wake up (The default configuration)

The enabling of the wake-up mode executes a partial enabling of the

receiver state machine. Even though the receiver has been reset the

wake up mode will over ride the disable and reset condition.

In the default (mode ‘00’ above and the least efficient) configuration

for this mode of operation, a ’master’ station transmits an address

character followed by data characters for the addressed ’slave’

station. The slave stations, whose receivers are normally disabled

(not reset), examine the received data stream. Upon recognition of

its address bit (this is the parity bit redefined to indicate the

associated byte is an address bye – not the address itself)

interrupts the CPU (by setting RxRDY). The CPU (host) compares

the received address to its station address and enables the receiver

if it wishes to receive the subsequent data characters. Upon receipt

of another address character, the CPU may disable the receiver to

initiate the process again.

A transmitted character consists of a start bit; the programmed

number of data bits, an address/data (A/D) bit and the programmed

number of stop bits. The CPU selects the polarity of the transmitted

A/D bit by programming bit MR1 [2]. MR1 [2] = 0 transmits a zero in

the A/D bit position which identifies the corresponding data bits as

data. MR1 [2] = 1 transmits a one in the A/D bit position which

identifies the corresponding data bits as an address. The CPU

should program the mode register prior to loading the corresponding

data bytes into the TxFIFO.

While in this mode, the receiver continuously looks at the received

data stream, whether it is enabled or disabled. If disabled, it sets the

RxRDY status bit and loads the character into the RxFIFO if the

received A/D bit is a one, but discards the received character if the

received A/D bit is a zero. If the receiver is enabled, all received

characters are transferred to the CPU via the RxFIFO. In either case

when the address character is recognized the data bits are loaded

into the data FIFO while the A/D bit is loaded into the status FIFO

position normally used for parity error (SR [5]). Framing error,

overrun error, and break detect operate normally whether or not the

receiver is enabled. When the automatic modes are in operation the

loading of the address character to the FIFO is controlled by the

MR0 (6) bit.

Philips Semiconductors Product data sheet

SC28L202Dual UART

2005 Nov 01

The several automatic controls. These modes are concerned with

the recognition of the address character itself

• MR3 [1:0] = 01 Auto wake. Enable receiver on address

recognition for this station. Upon recognition of its assigned

address the local receiver will be enabled by the character

recognition state machine and normal receiver communications

with the host will be established.

• MR3 [1:0] = 10 Auto Doze. Disable receiver on address

recognition, not for this station. Upon recognition of an address

character that is not its own, in the Auto Doze mode, the receiver

will be disabled by the character recognition state machine and

the address just received either discarded or loaded to the

RxFIFO depending on the programming of MR0 [6].

• MR3 [1:0] = 11 Auto wake and doze. Both modes described

above. The programming of MR3 [1:0] to 11 will enable both the

auto wake and auto doze features.

The enabling of the wake-up mode executes a partial enabling of the

receiver state machine. Even though the receiver has been reset the

wake up mode will over ride the disable and reset conditions.

Receiver Reset and Disable

Receiver disable stops the receiver immediately – data being

assembled in the receiver shift register is lost. Data and status in the

FIFO is preserved and may be read. A re-enable of the receiver

after a disable will cause the receiver to begin assembling

characters at the next start bit detected.

Receiver reset will discard the present shift register data, reset the

receiver ready bit (RxRDY), clear the status of the byte at the top of

the FIFO and re-align the FIFO read/write pointers. This effectively

‘clears’ the receiver FIFO although the FIFO data is not altered.

Receiver Watchdog Timer

A ‘watchdog timer’ is associated with each receiver. Its interrupt is

enabled by the ‘watchdog’ bits of the ‘Watch Dog, Character

Address, and X enable’ register (WCXER). The purpose of this timer

is to alert the control processor that characters are in the RxFIFO

which have not been read and/or the data stream has stopped. This

situation may occur at the end of a transmission when the last few

characters received are not sufficient to cause an interrupt. This

counter times out after 64 bit times. It is reset each time a read of

the RxFIFO is executed.

Receiver Time-out Mode

In addition to the watch dog timer described in the receiver section,

the counter/timer may be used for a similar function. Its

programmability, of course, allows much greater precision of timeout

intervals.

The time-out mode uses the received data stream to control the

counter. Each time a received character is transferred from the shift

not received before the counter reaches zero count, the counter

ready bit is set, and an interrupt can be generated. This mode can

be used to indicate when data has been left in the RxFIFO for more

than the programmed time limit. Otherwise, if the receiver has been

programmed to interrupt the CPU when the receive FIFO is full, and

the message ends before the FIFO is full, the CPU may not know

there is data left in the FIFO. The CTPU and CTPL value would be

programmed for just over one character time, so that the CPU would

be interrupted as soon as it has stopped receiving continuous data.

This mode can also be used to indicate when the serial line has

been marking for longer than the programmed time limit. In this

case, the CPU has read all of the characters from the FIFO, but the

last character received has started the count. If there is no new data

during the programmed time interval, the counter ready bit will get

set, and an interrupt can be generated.

Writing the appropriate command to the command register enables

the time-out mode. Writing an ‘Ax’ to CR A or CR B will invoke the

time-out mode for that channel. Writing a 0xCx to CR A or CR B will

disable the time-out mode. CTPU and CTPL should be loaded with a

count-down value that, with the selected clock, will generate a time

period greater than the normal receive character period. The

time-out mode disables the regular START/STOP Counter

commands and puts the C/T into counter mode under the control of

the received data stream. Each time a received character is

transferred from the shift register to the RxFIFO, the C/T is stopped

after 1 C/T clock, reloaded with the value in CTPU and CTPL and

then restarted on the next C/T clock. If the C/T is allowed to end the

count before a new character has been received, the counter ready

bit, ISR [3], will be set. If IMR [3] is set, interrupt arbitration for the

C/T will begin. Invoking the ‘Set Time-out Mode On’ command, CRx

= ‘Ax’, clears the counter ready bit and stop the counter until the

next character is received.

Exiting the time mode will clear the counter ready bit.

Arbitrating Interrupt Structure

(NOTE: The advantages and intelligence of this system may be

completely defeated by merely setting the arbitration value in the

ICR to 0x00 and not using the CIR. One would then rely on

traditional interrupt service by searching and testing various status

registers on the assertion of the IRQN.)

The interrupt system determines when an interrupt should be

asserted thorough an arbitration (or bidding) system. This arbitration

is exercised over the several systems within the DUART that may

generate an interrupt. These will be referred to as ‘interrupt sources’.

There are 18 in all and may of those have several sub-levels. In

general the arbitration is based on the fill level of the receiver FIFO

or the empty level of the transmitter FIFO. The FIFO levels are

encoded into an 8-bit number, which is concatenated to the channel

number and source identification code. All of this is compared (via

the bidding or arbitration process) to a user defined ‘threshold’.

Whenever a source exceeds the numerical value of the threshold

the interrupt will be generated.

Interrupt sources that do not have a FIFO are each provided with a

‘programmable field’ that will determine their importance in the

arbitration and type identification process. (See Table 1 below)

At the time of interrupt acknowledge (IACKN) the source which has

the highest bid (not necessarily the source that caused the interrupt

to be generated) will be captured in a ‘Current Interrupt Register’

(CIR). This register will contain the complete definition of the

interrupting source: channel, types of interrupt (receiver, transmitter,

change of state, etc.) and FIFO fill level. The value of the bits in the

CIR are used to drive the interrupt vector and global registers such

that controlling processor may be steered directly to the proper

service routine. A single read operation to the CIR provides all the

information needed to qualify and quantify the most common

interrupt sources.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P69 P70-P72 P73-P75 P76-P77

SC28L202A1DGG,129

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NXP Semiconductors

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UART Interface IC 3-5V 2CH UART 3MBPS

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SC28L202A1DGG,129

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