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SC28L202A1DGG,129

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P77
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
13
The interrupt sources for each channel are listed below.
• Receiver without error
• Receiver with error for each channel
• Receiver Watch Dog Time-out Event
• Transmitter
• Change in break received status per channel
• Rx loop back error
• Change of state on channel input pins
• Xon/Xoff character recognition
• Counter-Timer
• Address character recognition
• No interrupt active (very useful in polled service and as a test
value to terminate interrupt service)
Transmit FIFO empty level and Receiver FIFO fill levels are unique
for each channel and may be set at any level.
Associated with the interrupt system are the interrupt mask register
(IMR) and the interrupt status register (ISR) resident in each UART.
Programming of the IMR selects which of the above sources may
enter the arbitration process. The IMR enables the interrupt. Only
the bidders in the ISR whose associated bit in the IMR is set to one
(1) will be permitted to enter the arbitration process. The ISR can be
read by the host CPU to determine all currently active interrupting
conditions. For convenience of reading the ISR the MR1 (6) bit,
when set, allows the reading of the ISR masked by the bits of the
IMR.
Enabling and Activating Interrupt sources
An interrupt source becomes enabled when writing a one to the
proper Interrupt Mask Register bit (IMR) activates its interrupt
capability. An interrupt source can never generate an IRQN or have
its ‘bid’ or interrupt number appear in the CIR unless the source has
been enabled by the appropriate bit in an IMR.
An interrupt source is active if it is presenting its bid to the interrupt
arbiter for evaluation. Most sources have simple activation
requirements. The watch-dog timer, break received, Xon/Xoff or
Address Recognition and change of state interrupts become active
when the associated events occur and the arbitration value
generated thereby exceeds the threshold value programmed in the
ICR (Interrupt Control Register).
The transmitter and receiver functions have additional controls to
modify the condition upon which the initiation of interrupt ‘bidding’
begins: the TxINT and RxINT fields of the MR0 and MR2 registers.
These fields can be used to start bidding or arbitration when the
RxFIFO is not empty, 50% full, 75% full or 100% full. For the
transmitter it is not full, 50% empty, 75% empty and empty.
Example: To increase the probability of transferring the contents of a
nearly full RxFIFO, do not allow it to start bidding until 50% or 75%
full. This will prevent its relatively high priority from winning the
arbitration process at low fill levels. A high threshold level could
accomplish the same thing, but may also mask out low priority
interrupt sources that must be serviced. Note that for fast channels
and/or long interrupt latency times using this feature should be used
with caution since it reduces the time the host CPU has to respond
to the interrupt request before receiver overrun occurs.
Setting interrupt priorities
The bid or interrupt number presented to the interrupt arbiter is
composed of character counts, channel codes, fixed and
programmable bit fields. The interrupt values are generated for
various interrupt sources as shown in Table 1. The value
represented by the bits 11 to 4 in Table 1 are compared against the
value represented by the ‘Threshold. The ‘Threshold’, bits 10 to 0 of
the ICR (Interrupt Control Register), is aligned such that bit 0 of the
threshold is compared to bit 1 of the interrupt value generated by
any of the sources. Whenever the value of the interrupt source is
greater than the threshold the interrupt will be generated.
The channel number arbitrates only against other channels. The
threshold is not used for the channel arbitration. This results in
channel B having the highest arbitration number. The decreasing
order is B to A. If all other parts of an arbitration cycle are equal then
the channel number will determine which channel will dominate in
the arbitration process.
Note several characteristics of Table 1 in bits 4:1. These bits contain
the identification of the bidding source as indicated below:
• x001 Receiver without error
• x101 Receiver with error (errors are: parity, framing and overrun.
Break is not considered an error.
• x100 Receiver Watch Dog
• x010 Transmitter
• 1110 Change of Break
• 1111 Rx Loop Back Error
• 0110 Change of State on I/O Ports
• 0111 Xon/Xoff Event
• 1000 Counter timer
• 1011 Address Recognition
• 0000 No interrupt source active
The codes form bits 4:1 drive part of the interrupt vector modification
and the Global Interrupt Type Register. The codes are unique to
each source type and identify them completely. The channel
numbering progresses from ‘A’ to ‘B’ as the binary numbers 0 to 1
and identify the interrupting channel uniquely. As the channels
arbitrate ‘B’ will have the highest bidding value and ‘A’ the lowest.
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
14
Table 1. Interrupt Values
Type Bit 11:4 Bit 3 Bit 2 Bit 1 Bit 0
Receiver w/o error RxFIFO filled Byte Count 0 0 1 Channel No.
Receiver w/ error RxFIFO filled Byte Count 1 0 1 Channel No.
Receiver Watch-dog RxFIFO filled Byte Count 1 0 0 Channel No.
Transmitter TxFIFO empty Byte Count 0 1 0 Channel No.
Change of Break Programmed Field 1 1 1 0 Channel No.
Rx Loop Back Error Programmed Field 1 1 1 1 Channel No.
Change of State Programmed Field 0 1 1 0 Port 0 or 1
Xon/Xoff Programmed Field 0 1 1 1 Channel No.
Counter timer Programmed Field 1 0 0 0 Counter 0 or 1
Address Recognition Programmed Field 1 0 1 1 Channel No.
No interrupt 0 0 0 0 0
Threshold Bits 7:0 of Interrupt Control Register (ICR) 0 0 0 0 0
Interrupt Arbitration and IRQN generation
Interrupt arbitration is the process used to determine that an
interrupt request should be presented to the host. The arbitration is
carried out between the ‘Interrupt Threshold’ and the ‘sources’
whose interrupt bidding is enabled by the IMR. The interrupt
threshold is part of the ICR (Interrupt Control Register) and is a
value programmed by the user. The ‘sources’ present a value to the
interrupt arbiter. That value is derived from four fields: the channel
number, type of interrupts source, FIFO fill level, and a
programmable value. The interrupt request (IRQN) will be asserted
only when one or more of these values exceeds the threshold value
in the interrupt control register will.
Following assertion of the IRQN the host will either assert IACKN
(Interrupt Acknowledge) or will use the command to ‘Update the
CIR’. At the time either action is taken the CIR will capture the value
of the source that is prevailing in the arbitration process. (Call this
value the winning bid).
The Sclk drives the arbitration process. It evaluates the 12 bits of
the arbitration bus at ½ the Sclk rate developing a value for the CIR
every two Sclk cycles. New arbitration values presented to the
arbitration block during an arbitration cycle will be evaluated in the
next arbitration cycle.
For sources other than receiver and transmitters the user may set
the high order bits of an interrupt source’s bid value, thus tailoring
the relative priority of the interrupt sources. The fill level of their
respective FIFOs controls the priority of the receivers and
transmitters. The more filled spaces in the RxFIFO the higher the bid
value; the more empty spaces in the TxFIFO the higher its priority.
Channels whose programmable high order bits are set will be given
interrupt priority higher than those with zeros in their high order bits,
thus allowing increased flexibility. The transmitter and receiver bid
values contain the character counts of the associated FIFOs as high
order bits in the bid value. Thus, as a receiver’s RxFIFO fills, it bids
with a progressively higher priority for interrupt service. Similarly, as
empty space in a transmitter’s TxFIFO increases, its interrupt
arbitration priority increases.
The programmable fields allow the software to adjust the authority or
value of the bid for those devices not having a FIFO.
For example: The break condition is sometimes used to signal a
starting point in a continuous stream of data. A Continuous running
weather report or stock market ‘ticker-tape’ report needs breaks in
the data so that a receiver knows where the data starts. Once start
of the break is detected it is important to reset the ‘change of break’
interrupt so that this bit can signal the condition of the break ending.
This is signaled by the ‘L202 the setting another change of break
event in the ISR. Since it is assumed the data will be starting very
soon after the end of break it is important to give the change of
break condition a high priority. This may be accomplished by setting
the arbitration value for the ‘change of break’ to a high value. The
value in the ‘change of break programmable field’ in Table 1 would
be 0x7F.
IACKN Cycle, Update CIR
When the host CPU responds to the interrupt, it will usually assert
the IACKN signal low. This will cause the DUART to generate an
IACKN cycle in which the condition of the interrupting device is
determined. When IACKN asserts, the last valid interrupt number is
captured in the CIR. The value captured presents most of the
important details of the highest priority interrupt at the moment the
IACKN (or the ‘Update CIR’ command) was asserted.
The Dual UART will respond to the IACKN cycle with an interrupt
vector. The interrupt vector may be a fixed value, the content of the
Interrupt Vector Register, or when ‘Interrupt Vector Modification’ is
enabled via ICR, it may contain codes for the interrupt type and/or
interrupting channel. This allows the interrupt vector to steer the
interrupt service directly to the proper service routine. The interrupt
value captured in the CIR remains until another IACKN cycle occurs
or until an ‘Update CIR’ command is given to the DUART. The
interrupting channel and interrupt type fields of the CIR set the
current ‘interrupt context’ of the DUART. The channel component of
the interrupt context allows the use of Global Interrupt Information
registers that appear at fixed positions in the register address map.
For example, a read of the Global RxFIFO will read the channel B
RxFIFO if the CIR interrupt context is channel B receiver. At another
time read of the GRxFIFO may read the channel A RxFIFO (CIR
holds a channel A receiver interrupt) and so on. Global registers
exist to facilitate qualifying the interrupt parameters and for writing to
and reading from FIFOs without explicitly addressing them.
The CIR will load with x’00 if IACKN or Update CIR is asserted when
the arbitration circuit is NOT asserting an interrupt. In this condition
there is no arbitration value that exceeds the threshold value. When
Interrupt vector modification is active in this situation the interrupt
vector bits associated with the CIR will all be zero.
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
15
Global Registers
The ‘Global Registers’, 10 in all, are driven by the interrupt system.
They are defined by the content of the CIR (Current Interrupt
Register) as a result of an interrupt arbitration. In other words they
are indirect registers pointed to by the content of the CIR. The list of
global register follows:
• GIBCR The byte count of the interrupting FIFO
• GICR Channel number of the interrupting channel
• GITR Type identification of interrupting channel
• GRxFIFO Pointer to the interrupting receiver FIFO
• GTxFIFO Pointer to the interrupting transmitter FIFO
A read of the GRxFIFO will give the content of the RxFIFO that
presently has the highest bid value. The purpose of this system is to
enhance the efficiency of the interrupt system. The global registers
and the CIR update procedure are further described in the Interrupt
Arbitration system
Polling, (Normal and using the CIR)
The ‘arbitrating interrupt system’ will reduce the polling overhead to
only two bus cycles. It only requires an update CIR command and a
CIR read to find if service is needed, and if needed to show what
needs to be serviced.
Many users prefer polled to interrupt driven service where there are
not a large number of fast data channels and/or the host CPU’s
other interrupt overhead is low. The Dual UART is functional in this
environment.
The most efficient method of polling is the use of the ‘update CIR’
command (with the interrupt threshold set to zero) followed by a
read of the CIR. This dummy write cycle will perform the same CIR
capture function that an IACKN falling edge would accomplish in an
interrupt driven system. A subsequent read of the CIR, at the same
address, will give information about an interrupt, if any. If the CIR
type field contains 0s, no interrupt is awaiting service. If the value is
non-zero, the fields of the CIR may be decoded for type; channel
and character count information. Optionally, the global interrupt
registers may be read for particular information about the interrupt
status or use of the global RxD and TxD registers for data transfer
as appropriate. The interrupt context will remain in the CIR until
another update CIR command or an IACKN cycle is initiated by the
host CPU occurs. The CIR loads with x’00 if Update CIR is asserted
when the arbitration circuit has NOT detected an arbitration value
that exceeds the threshold value of the ICR. The global registers
and CIR may be used as ‘vectors’ to the service type required.
Traditional methods of polling status registers may also be used.
Their lower efficiency may be greatly offset by use of the UCIR
command and the read of the CIR. They reduce the many reads and
tests of status registers to only one read and one write. This would
normally be accomplished by setting the interrupt threshold to zero.
Then the moment any system within the DUART needs service the
next poll of the CIR would return a non zero value and the type field
will inform the processor which of the possible 18 systems needs
service. In the case of the FIFOs the number of bytes to be written
or read is also available.
Character and Address Recognition
(Also used for Multi-drop, Xon/Xoff systems)
Character recognition is specific to each of the two UARTs. Three
programmable characters are provided for the character recognition
for each channel. The three are general purpose in nature and may
be set to only cause an interrupt or to initiate some rather complex
operations specific to ‘Multi-drop’ address recognition or in-band
Xon/Xoff flow control.
Character recognition system continually examines the incoming
data stream. Upon the recognition of a character bits appropriate for
the character recognized are set in the Xon/Xoff Interrupt Status
Register (XISR) and in the Interrupt Status Register (ISR). The
setting of these bit(s) will initiate any of the automatic sequences or
and/or an interrupt that may have enabled via the MR3 register.
NOTE: Reading the XISR Clears the status bits associated with the
recognition.
The characters of the recognition system are fully programmable.
The Xon/Xoff characters will be set to the standard characters if the
hardware or software reset is used.
The character recognition circuits are basically designed to provide
general-purpose character recognition. Additional control logic has
been added to allow for Xon/Xoff flow control and for recognition of
the address character in the multi-drop or ‘wake-up’ mode. This logic
also allows for the generation of interrupts in either the
general-purpose recognition mode or the specific conditions
mentioned above.
The generality of the above provides a modicum of compatibility to
BOP (Bit Oriented Protocol) where the generation and detection of
‘flags’ is required. Parts of usually synchronous BOP protocols
(HDLC in particular) are beginning to show up in asynchronous
formats.
Character Stripping
The MR0[7:6] register provides for stripping the characters used for
character recognition. Recall that the character recognition may be
conditioned to control several aspects of the communication.
However this system is first a character recognition system. The
status of the various states of this system is reported in the XISR
and ISR registers. The character stripping of this system allows for
the removal of the specified control characters from the data stream:
two for the Xon /Xoff and one for the wake up. Via control in the
MR0[7:6] register these characters may be discarded (stripped) from
the data stream when the recognition system ‘sees’ them or they
may be sent on the RxFIFO. Whether they are stripped or not the
recognition system will process them according to the action
requested; flow control, wake up, interrupt generation, etc. Care
should be exercised in programming the stripping option if noisy
environments are encountered. If a normal character were corrupted
to a Xoff character the transmitter would be stopped. If that
character were now stripped from the FIFO stack, then that stripping
action would make it difficult to determine the cause of transmitter
stopping.
When character stripping is invoked and a recognition character is
received that has an error bit set that character is sent to the
RxFIFO even though character stripping is active.
Flow Control (Xon/Xoff)
This section describes in-band flow control or Xon/Xoff signaling.
For the RTS/CTS hardware (out-of-band) control see MR1(7) and
MR2(4) descriptions.
The flow control is accomplished via the character recognition
system giving recognition information to the flow control processor.
Xon and Xoff are special characters used by a receiver to start and
stop the remote transmitter that is sending it data. As described
below several modes of manual and automatic flow control are
available by program control.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P77

SC28L202A1DGG,129

Mfr. #:
Buy SC28L202A1DGG,129
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 3-5V 2CH UART 3MBPS
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New from this manufacturer.
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