Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
33
CTPU Counter Timer Preset Upper 0 and 1
CTPU
Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
The lower eight (8) bits for the 16 bit counter timer preset register
CTPL Counter –Timer Preset Low 0 and 1
CTPL
Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
The Upper eight (8) bits for the 16 bit counter timer preset register
The CTPU and CTPL hold the eight MSBs and eight LSBs,
respectively, of the value to be used by the counter/timer in either
the counter or timer modes of operation. The minimum value that
may be loaded into the CTPU/CTPL registers is H‘0000’. Note that
these registers are write–only and cannot be read by the CPU.
In the timer mode, the C/T generates a square wave whose period is
twice the value (in C/T clock periods) of the CTPU and CTPL. The
waveform so generated is often used for a data clock. The formula
for calculating the divisor n to load to the CTPU and CTPL for a
particular 1X data clock is shown below.
NOTE: The 2 in the denominator is for the Square wave generation.
For the Pulse mode change the 2 to a 1.
n +
C/T clock input frequency
(2 16 (Baud rate desired))
(If the pulse mode is selected, then ‘2’ in the divisor should be ‘1’.
This doubles the C/T output speeds for any given input clock.)
Often this division will result in a non–integer number, 26.3 for
example. One can only program integer numbers in a digital divider.
Therefore, 26 would be chosen. This gives a baud rate error of
0.3/26.3, which is 1.14% and well within the ability asynchronous
mode of operation.
If the value in CTPU and CTPL is changed, the current half–period
will not be affected, but subsequent half periods will be. The C/T will
not be running until it receives an initial ‘Start Counter’ command
from the command register (or a read at address A6–A0 = 0001110
in the lower 16 position address space) . After this, while in timer
mode, the C/T will run continuously. Receipt of a start counter
command causes the counter to terminate the current timing cycle
and to begin a new cycle using the values in CTPU and CTPL.
The counter ready status bit (ISR [3]) is set once each cycle of the
square wave. The bit is reset by a stop counter command from the
command register (or a read with A6–A0 = 0x0F in the lower 16
position address space). The command however, does not stop the
C/T. the generated square wave is output on I/O3 if it is programmed
to be the C/T output. In the counter mode, the value C/T loaded into
CTPU and CTPL by the CPU is counted down to 0. Counting begins
upon receipt of a start counter command. Upon reaching terminal
count H‘0000’, the counter ready interrupt bit (ISR [3]) is set. The
counter continues counting past the terminal count until stopped by
the CPU. If I/O3 is programmed to be the output of the C/T, the
output remains high until terminal count is reached; at which time it
goes low. The output returns to the High State and ISR [3] is cleared
when the counter is stopped by a stop counter command. The CPU
may change the values of CTPU and CTPL at any time, but the new
count becomes effective only on the next start counter commands. If
new values have not been loaded, the previous count values are
preserved and used for the next count cycle
In the counter mode, the current value of the upper and lower 8 bits
of the counter (CTPU, CTPL) may be read by the CPU. It is
recommended that the counter be stopped when reading to prevent
potential problems that may occur if a carry from the lower 8 bits to
the upper 8 bits occurs between the times that both halves of the
counter are read. However, note that a subsequent start counter
command will cause the counter to begin a new count cycle using
the values in CTPU and CTPL. When the C/T clock divided by 16 is
selected, the maximum divisor becomes 1,048,575.
The CTS, RTS, CTS Enable Tx signals
CTS (Clear To Send) is usually meant to be a signal to the
transmitter meaning that it may transmit data to the receiver. The
CTS input is on pin I/O0 A for Tx A and on I/O1 A for Tx B. The CTS
signal is active low; thus; it is called CTSN A for Tx A and CTSN B
for Tx B. RTS is usually meant to be a signal from the receiver
indicating that the receiver is ready to receive data. It is also active
low and is, thus, called RTSN A for Rx A and RTSN B for Rx B.
RTSN A is on pin I/O0 B and RTSN B is on I/O1 B. A receiver’s
RTSN output will usually be connected to the CTS input of the
associated transmitter. Therefore, one could say that RTS and CTS
are different ends of the same wire!
MR2 (4) is the bit that allows the transmitter to be controlled by the
CTS pin (I/O0 A or I/O1 A). When this bit is set to one AND the CTS
input is driven high, the transmitter will stop sending data at the end
of the present character being serialized. It is usually the RTS output
of the receiver that will be connected to the transmitter’s CTS input.
The receiver will set RTS high when the receiver FIFO is full AND
the start bit of the ninth character is sensed. Transmission then
stops with nine valid characters in the receiver. When MR2 (4) is set
to one, CTSN must be at zero for the transmitter to operate. If MR2
(4) is set to zero, the I/O pin will have no effect on the operation of
the transmitter. MR1 (7) is the bit that allows the receiver to control
I/O0 B. When the receiver controls I/O0 B (or I/O1 B), the meaning
of that pin will be the RTSN function.
