Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
39
THE REGISTERS FOR COMPATIBILITY WITH PREVIOUS DUARTS
The purpose of including previous functionality is to allow users to
call communications code that may be used in former systems.
When the registers in this lower 16–position address space is used
it will revoke programming done in the upper address space where
the addresses are duplicated. If functions have been called from
upper address space that DO NOT exist in the lower address space
they will remain active. It is therefore recommended that the ‘Reset
to C92’ command be issued before calling code written for older
devices. This is just recommended. If one wishes to enhance
previous code by using Xon/Xoff, for example, there is no restriction
against it. These registers provide the original functionality of
previous Philips DUARTs: SCN2681, SCN68681, SCC2691,
SCC68692, SC26C92 and SC28L92.
Table 7. SC28L92 Register Addressing READ (RDN = 0) WRITE (WRN = 0)
Address READ (RDN = 0) WRITE (WRN = 0)
0 0 0 0 Mode Register A (MR0 A, MR1 A, MR2 A) Mode Register A (MR0 A, MR1 A, MR2 A)
0 0 0 1 Status Register A (SR A) Clock Select Register A (CSR A )
0 0 1 0 Reserved Command Register A (CR A)
0 0 1 1 Rx Holding Register A (RxFIFO A) Tx Holding Register A (TxFIFO A)
0 1 0 0 Input Port Change Register (IPCR) Aux. Control Register (ACR)
0 1 0 1 Interrupt Status Register (ISR) Interrupt Mask Register (IMR)
0 1 1 0 Counter/Timer Upper (CTPU) C/T Upper Preset Register (CTPU)
0 1 1 1 Counter/Timer Lower (CTPL) C/T Lower Preset Register (CTPL)
1 0 0 0 Mode Register B (MR0 B, MR1 B, MR2 B) Mode Register B (MR0 B, MR1 B, MR2 B)
1 0 0 1 Status Register B (SR B) Clock Select Register B (CSR B )
1 0 1 0 Reserved Command Register B (CR B)
1 0 1 1 Rx Holding Register B (RxFIFO B) Tx Holding Register B (TxFIFO B)
1 1 0 0 IVR or general purpose register IVR or general purpose register
1 1 0 1 Input Port (IPR) I/O(6:0) A Output Port Confide. Register (OPCR) I/O(7:2) B
1 1 1 0 Start Counter Command (C/T 0) Set Output Port Bits Command (SOPR) I/O(7:0) B
1 1 1 1 Stop Counter Command (C/T 0) Reset output Port Bits Command (ROPR) I/O(7:0) B
NOTE: The three MR Registers are accessed via the MR Pointer and Commands 0x1n and 0xBn (where n = represents receiver and
transmitter enable bits)
The following registers are unique for each Channel
Mode Register MRn A MRn B R/W
Status Register SR A SR B R only
Clock
Select
CSR A CSR B W only
Command
Register
CR A CR B W only
Receiver
FIFO
RxFIFO A RxFIFO B R only
Transmitter
FIFO
TxFIFO A TxFIFO B W only
These registers support functions for both Channels
Input Port Change Register IPCR R
Auxiliary Control Register ACR W
Interrupt Status Register ISR R
Interrupt Mask Register IMR W
Counter Timer Upper Value CTPU R
Counter Timer Lower Value CTPL R
Counter Timer Preset Upper CTPU W
Counter Timer Preset Lower CTPL W
Input Port Register IPR R
Output Configuration Register OPCR W
Set Output Port Bits W
Reset Output Port Bits W
