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SC28L202A1DGG,129

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P77
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
61
SD00734
CEN
RDN, RWN
Intel-type bus:
Active area
CEN
RDN, WRN
CEN
RDN, WRN
CEN
RDN, WRN
Motorola-type:
Active area
CEN
RWN (Write)
RWN (Read)
DACKN
not used
CEN
RWN
DACKN
When DACK
controls
NOTE: In the 68K mode, the write occurs on the rise of CEN or fall of DACKN, whichever occurs first.
Figure 3. Active area in 68K mode.
If you have further questions, please direct them to the factory contact:
datacom.tech-support@philips.com
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
62
RESETN
t
RES
SD00729
Figure 4. Reset Timing (80XXX mode)
RESETN
t
RES
SD00109
Figure 5. Reset Timing (68XXX mode)
A0–A3
CEN
t
AS
t
CS
t
CH
RDN
t
RW
t
RWD
D0–D7
(READ)
t
DD
t
DF
FLOAT FLOATVALID
NOT
VALID
WDN
t
RWD
VALID
D0–D7
(WRITE)
t
DS
t
DH
t
AH
SD00087
Figure 6. Bus Timing (80XXX mode)
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
63
X1/CLK
A1–A4
RWN
CEN
D0–D7
DACKN
t
CSC
t
AS
t
CS
t
DF
t
DAT
t
CH
t
RWD
t
DD
t
DCR
t
AH
DATA VALID
NOT
VALID
t
DA
NOTE: DACKN low requires two rising edges of X1 clock after CEN is low.
SD00730
Figure 7. Bus Timing (Read Cycle) (68XXX mode)
X1/CLK
A1–A4
RWN
CEN
D0–D7
DACKN
t
CSC
t
AS
t
CS
t
DH
t
DAT
t
CH
t
RWD
t
DS
t
DCW
t
AH
NOTE: DACKN low requires two rising edges of X1 clock after CEN is low.
SD00731
Figure 8. Bus Timing (Write Cycle) (68XXX mode)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P77

SC28L202A1DGG,129

Mfr. #:
Buy SC28L202A1DGG,129
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 3-5V 2CH UART 3MBPS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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