Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
60
LIMITS
4
Symbol UNITMaxTypMinParameter
68000 or Motorola bus timing (See Figures 7, 8, 9)
t
CS(mot)
RWN set-up time to CEN LOW 5 – – ns
t
DS(mot)
Data bus set-up time before X1 HIGH 10 – – ns
t
DH(mot)
Data hold time after CEN HIGH 0 – – ns
t
AS(mot)
Address set-up time to CEN LOW 10 – – ns
t
AH(mot)
Address hold time from CEN LOW 10 – – ns
t
DD(mot)
Data valid after CEN LOW – – 45 ns
t
RWD(mot)
HIGH time between read and/or write cycles
5,
7
10 – – ns
t
DCR
DACKN Low (read cycle) from X1 High – – 35 ns
T
DCW
DACKN Low (write cycle) from X1 High – – 30 ns
t
DAT
DACKN High impedance from CEN or IACKN high – – 15 ns
t
CSC
CEN or IACKN set-up time to X1 high for minimum DACKN cycle 10 – – ns
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
5 ns maximum. For X1/SCLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of 0.8 V and
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
3. Test conditions for outputs: C
L
= 85 pF, except interrupt outputs. Test conditions for interrupt outputs: C
L
= 85 pF, R
L
= 2.7 kΩ to V
CC
.
4. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.
5. Timing is illustrated and referenced to the WRN and RDN inputs. Also, CEN may be the ‘strobing’ input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. Guaranteed by characterization of sample units.
7. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for t
RWD
time to guarantee that any status register changes are valid.
8. Minimum frequencies are not tested but are guaranteed by design.
9. Clocks for 1X mode should be reasonably symmetrical.
10.Data is usually set up with respect to CEN going LOW—the leading edge of CEN. This mode strongly implies the use of DACKN. (Its use is
not strictly required.) DACKN is derived from the X1/SCLK input. It is seldom that the system clocks that ultimately drive the CEN, address
and RWN signals are synchronous to the X1/SCLK. If address, data, RWN are set up before CEN goes LOW and hold through DACKN, the
timing parameters above will be guaranteed.
TIMING DIAGRAMS
The active time of read or write cycle exists only when CEN is LOW
and RDN or CEN is also LOW.
Write = CEN and WRN LOW.
Read = CEN and RDN LOW.
For the 68K mode:
Write = CEN LOW and RWN LOW and DACKN HIGH.
Read = CEN LOW and RWN HIGH.
In general, it is convenient (but is not at all required) to think of the
Read/Write signal to be active and then let the CEN be the ‘strobing’
or clocking control. However, some users have wired CEN LOW and
allowed RDN or WRN to be the clocking or ‘strobing’ input. While
this is completely within the specified limits, it is not recommended
since it will greatly increase the part’s sensitivity to noise ‘glitches’
on the RDN and WRN signals.
For the 68K mode, the CEN is very much the clock or ‘strobing’
signal. The RDN and WRN signals have been combined into the
RWN signal. Therefore, the part is always prepared to do a write or
read—it only needs CEN to enable.
In the 68K mode design, care should be given to system drift over
temperature, voltage, and age when RWN and CEN change very
close to each other. If RWN switches shortly before CEN (due to
system drift) it is possible to produce very short internal read or write
pulses which could change internal controls, FIFO address pointers,
for example.
Figure 3 loosely shows the timing conditions that may exist of the
active area those signals will produce.
