Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
34
Registers of the Arbitrating Interrupt System and Bidding control
ICR – Interrupt Control Register
Bits 7:0
Upper eight bits of the Arbitration Threshold
This register provides a single 8–bit field called the interrupt
threshold for use by the interrupt arbiter. The field is interpreted as a
single unsigned integer. The interrupt arbiter will not generate an
external interrupt request, by asserting IRQN, unless the value of
the highest priority interrupt exceeds the value of the interrupt
threshold. If the highest bidder in the interrupt arbitration is lower
than the threshold level set by the ICR, the Current Interrupt
Register, CIR, will contain 0x’00. Refer to the functional description
of interrupt generation for details on how the various interrupt source
bid values are calculated.
NOTE: While a watch–dog Timer interrupt is pending, the ICR is not
used and only receiver codes are presented for interrupt arbitration.
This allows receivers with very low count values (perhaps below the
threshold value) to win interrupt arbitration without requiring the user
to explicitly lower the threshold level in the ICR. These bits are the
upper seven (8) bits of the interrupt arbitration system. The lower
three (3) bits represent the channel number.
UCIR – Update CIR
A command based upon a decode of address 0x61. (UCIR is not a
register!) A write (the write data is not important; a ‘don’t care’) to
this ’register’ causes the Current Interrupt Register to be updated
with the value that is winning interrupt arbitration. The register would
be used in systems that polls the interrupt status registers rather
than wait for interrupts. Alternatively, the CIR is normally updated
during an Interrupt Acknowledge Bus cycle in interrupt driven
systems.
CIR – Current Interrupt Register
Bits 7:6 Bits 5:1 Bits 0
Type Current byte count/type Channel number or C/T number
00 = Type other than transmit or Receiver 00000 = no interrupt
00001 = Change of State
00010 = Address Recognition
00011 = Xon/Xoff status
00100 = Receiver Watch dog
00101 = Break change
00110 = Counter Timer
00111 = Rx Loop Back Error
0 = Channel A or C/T 0
1 = Channel B or C/T 1
01 = Transmit
11 = Receive w errors
10 = Receive w/o errors
Current count code
00000 => At least 1 character
00001 => At least 16 characters
00001 => At least 24 characters
.
.
11101 => At least 240 characters
11110 => At least 248 characters
11111 => 256 (See also GIBCR)
0 = A
1 = B
The Current Interrupt Register is provided to speed up the
specification of the interrupting condition in the DUART. The CIR is
updated at the beginning of an interrupt acknowledge bus cycle or in
response to an Update CIR command. (see immediately above)
Although interrupt arbitration continues in the background, the
current interrupt information remains frozen in the CIR until another
IACKN cycle or Update CIR command occurs. The LSBs of the CIR
provide part of the addressing for various Global Interrupt registers
including the GIBCR, GICR, GITR and the Global RxFIFO and
TxFIFO FIFO. The host CPU need not generate individual
addresses for this information since the interrupt context will remain
stable at the fixed addresses of the Global Interrupt registers until
the CIR is updated. For most interrupting sources, the data available
in the CIR alone will be sufficient to set up a service routine.
The CIR may be processed as follows:
If CIR[7] = 1, then a receiver interrupt is pending and the count is
CIR[5:1], channel is CIR[0]
Else If CIR[6] = 1 then a transmitter interrupt is pending and the
count is CIR[5:1], channel is CIR[0]
Else the interrupt is another type, specified in CIR[5:1]
NOTE: The GIBCR, Global Interrupting Byte Count Register, may be
read to determine an exact character count.
