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SC28L202A1DGG,129

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P77
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
49
OPCR Output Port Configuration Register. Controls [7:2] B
Bit 7 BIT 6 BIT 5 BIT 4 BIT (3:2) BIT (1:0)
I/O7 B I/O6 B I/O5 B I/O4 B I/O3 B I/O2 B
0 = OPR[7]
1 = Tx RDY B
0 = OPR[6]
1 = Tx RDY A
0 = OPR[5]
1 = Rx RDY / FFULL B
0 = OPR[4]
1 = Rx RDY / FFULL A
00 = OPR[3]
01 = C/T OUTPUT
10 = TxC B(1X)
11 = RxC B(1X)
00 = OPR[2]
01 = TxC A(16X)
10 = TxC A(1X)
11 = RxC A(1X)
NOTE: I/O0 B and I/O1 B output OPR(0) and OPR(1) respectively.
Under program control of MR1 and MR2 the signals RTSN A for
I/O0 B and RTSN B for I/O1 B may be assigned.
OPCR[7] – This bit programs the I/O7 B output to provide one of the
following:
• 0 The complement of OPR[7].
• 1 The Channel B transmitter interrupt output which is the
complement of ISR[4]. When in this mode I/O7 acts as an open–
drain output. Note that this output is not masked by the contents
of the IMR.
OPCR[6] – This bit programs the I/O6 B output to provide one of the
following:
• 0 The complement of OPR[6].
• 1 The Channel A transmitter interrupt output which is the
complement of ISR[0]. When in this mode I/O6 acts as an open–
drain output. Note that this output is not masked by the contents
of the IMR.
OPCR[5] – This bit programs the I/O5 B output to provide one of the
following:
• 0 The complement of OPR[5].
• 1 The Channel B receiver interrupt output which is the
complement of ISR[5]. When in this mode I/O5 acts as an
open–drain output. Note that this output is not masked by the
contents of the IMR.
OPCR[4] – This field programs the I/O4 B output to provide one of
the following:
• 0 The complement of OPR[4].
• 1 The Channel A receiver interrupt output which is the
complement of ISR[1]. When in this mode I/O4 acts as an
open–drain output. Note that this output is not masked by the
contents of the IMR.
OPCR[3:2] – This bit programs the I/O3 B output to provide one of
the following:
• 00 The complement of OPR[3].
• 01 The counter/timer output, in which case I/O3 acts as an
open–drain output. In the timer mode, this output is a square wave
at the programmed frequency. In the counter mode, the output
remains high until terminal count is reached, at which time it goes
low. The output returns to the high state when the counter is
stopped by a stop counter command. Note that this output is not
masked by the contents of the IMR.
• 10 The 1X clock for the Channel B transmitter that shifts the
transmitted data. If data is not being transmitted, a free running 1X
clock is output.
• 11 The 1X clock for the Channel B receiver that samples the
received data. If data is not being received, a free running 1X
clock is output.
OPCR[1:0] – This field programs the I/O2 B output to provide one of
the following:
• 00 The complement of OPR[2].
• 01 The 16X clock for the Channel A transmitter. This is the clock
selected by CSR A [3:0], and will be a 1X clock if CSR A [3:0] =
1111.
• 10 The 1X clock for the Channel A transmitter that shifts the
transmitted data. If data is not being transmitted, a free running 1X
clock is output.
• 11 The 1X clock for the Channel A receiver that samples the
received data. If data is not being received, a free running 1X
clock is output.
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
50
SOPR – Set Bits in the OPR
Ones in the byte written to this register will cause the corresponding bit positions in the OPR to set to 1. Zeros have no effect. This allows
software to set individual bits without keeping a copy of the OPR bit configuration.
Set OPR
Bits
Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
I/O7 B I/O6 B I/O5 B I/O4 B I/O3 B I/O2 B I/O1 B I/O0 B
1=set bit
0=no change
1=set bit
0=no change
1=set bit
0=no change
1=set bit
0=no change
1=set bit
0=no change
1=set bit
0=no change
1=set bit
0=no change
1=set bit
0=no change
ROPR – Reset Bits in the OPR
Ones in the byte written to the ROPR will cause the corresponding bit positions in the OPR to set to 0. Zeros have no effect. This allows
software to reset individual bits with our keeping a copy of the OPR bit configuration.
Reset OPR
Bits
Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
I/O7 B I/O6 B I/O5 B I/O4 B I/O3 B I/O2 B I/O1 B I/O0 B
1=reset bit
0=no change
1=reset bit
0=no change
1=reset bit
0=no change
1=reset bit
0=no change
1=reset bit
0=no change
1=reset bit
0=no change
1=reset bit
0=no change
1=reset bit
0=no change
OPR Output Port Register
The bits in the OPR register are controlled by the use of the SOPR and ROPR commands. The output pins (OP pins) drive the compliment of
the data stored in this register.
OPR
Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
I/O7 B I/O6 B I/O5 B I/O4 B I/O3 B I/O2 B I/O1 B I/O0 B
0=Pin High
1=Pin Low
0=Pin High
1=Pin Low
0=Pin High
1=Pin Low
0=Pin High
1=Pin Low
0=Pin High
1=Pin Low
0=Pin High
1=Pin Low
0=Pin High
1=Pin Low
0=Pin High
1=Pin Low
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
51
REGISTER MAPS
The registers of the SC28L202 are loosely partitioned into two
groups: those used in controlling data channels and those used in
handling the actual data flow and status. Below is shown the general
configuration of all the register addressed. The ‘Register Map
Summary’ shows the configuration of the lower four bits of the
address that is the same for the individual UARTs. It also shows
the addresses for the several in the address space of UART A and
UART B that apply to the total chip configuration. The ‘Register Map
Detail’ shows the use of every address in the 8–bit address space.
Any programming using the SC28L202 as it is intended would
always use the address space form 0x10 through 0x7F. For the
most part, differences in address between channel A and B differ by
0x08.
The first address from 0x00 to 0x0F refer to the legacy code for
previous Philips/Signetics two channel UARTs (DUARTs). This
feature is directed to the SC26C92. That part has 89-byte FIFOs,
but powers up to look like it has a 3-byte receiver FIFO and a 1-byte
transmitter FIFO. Other control registers structures of legacy parts
are compatible back to the SCN2681.
Registers that configure the whole chip are denoted by a ‘•’
symbol.
REGISTER MAP DETAIL (based on 28L92)
NOTE: Addresses 0x00 to 0x0F represent the ‘C92 Register’ map.
A[6:0]
READ WRITE
DEFAULT. The first 16 read and write locations are legacy code for other ’92-type UARTs.
000 0000 (0x00) Mode Register (MR0 A, MR1 A, MR2 A) DEFAULT Mode Register (MR0 A, MR1 A, MR2 A) DEFAULT
000 0001 (0x01) Status Register (SR A) Clock Select Register (CSR A) DEFAULT
000 0010 (0x02) Command Register (CR A) DEFAULT
000 0011 (0x03) Receiver FIFO Register (RxFIFO A) Transmitter FIFO Register (TxFIFO A)
000 0100 (0x04) Input Port Change Register (IPCR) DEFAULT • Auxiliary Control Register (ACR) DEFAULT
000 0101 (0x05) • Interrupt Status Register (ISR) DEFAULT • Interrupt Mask Register (IMR) DEFAULT
000 0110 (0x06) Counter Timer Value Register Upper (CTVU 0) Counter Timer Preset Register Upper (CTPU 0)
000 0111 (0x07) Counter Timer Value Register Lower (CTVL 0) Counter Timer Preset Register Lower (CTPL 0)
000 1000 (0x08) Mode Register (MR0 B, MR1 B, MR2 B) DEFAULT Mode Register (MR0 B, MR1 B, MR2 B) DEFAULT
000 1001 (0x09) Status Register (SR B) Clock Select Register (CSR B) DEFAULT
000 1010 (0x0A) Command Register (CR B) DEFAULT
000 1011 (0x0B) Receiver FIFO Register (RxFIFO B) Transmitter FIFO Register (TxFIFO B)
000 1100 (0x0C) • Interrupt Vector Register (IVR) GLOBAL • Interrupt Vector Register (IVR) GLOBAL
000 1101 (0x0D) Input Port Register (IPR) I/O(6:0) A Output Port Configuration Register (OPCR) I/O(7:2)B
000 1110 (0x0E) Start Counter Command DEFAULT C/T 0 Set Output Port Register (SOPR) I/O(7:0)B
000 1111 (0x0F) Stop Counter Command DEFAULT C/T 0 Reset Output Port Register (ROPR) I/O(7:0)B
EXTENSION
001 0000 (0x10) Receiver FIFO Fill Level (RxFL A) Set Output Port Register (SOPR A)
001 0001 (0x11) Transmitter FIFO Empty level (TxEL A) Reset Output Port Register (ROPR A)
001 0010 (0x12) • Enhanced Operation Status (EOS) Command Register Extension (CRx A)
001 0011 (0x13) Input Port Change Register Upper (IPCRU A) I/O Port Configuration Register 0 (I/OPCR 0)
001 0100 (0x14) Input Port Change Register Lower (IPCRL A) I/O Port Configuration Register 1 (I/OPCR 1)
001 0101 (0x15) Input Port Register (IPR A)
001 0110 (0x16) Counter Timer Value Register Upper (CTVU 0) Counter Timer Preset Register Upper (CTPU 0)
001 0111 (0x17) Counter Timer Value Register Lower (CTVL 0) Counter Timer Preset Register Lower (CTPL 0)
001 1000 (0x18) Receiver FIFO Fill Level (RxFL B) Set Output Port Register (SOPR B)
001 1001 (0x19) Transmitter FIFO Empty level (TxEL B) Reset Output Port Register (ROPR B)
001 1010 (0x1A) Command Register Extension (CRx B)
001 1011 (0x1B) Input Port Change Register Upper (IPCRU B) I/O Port Configuration Register 2 (I/OPCR 2)
001 1100 (0x1C) Input Port Change Register Lower (IPCRL B) I/O Port Configuration Register 3 (I/OPCR 3)
001 1101 (0x1D) Input Port Register (IPR B)
001 1110 (0x1E) Counter Timer Value Register Upper (CTVU 1) Counter Timer Preset Register Upper (CTPU 1)
001 1111 (0x1F) Counter Timer Value Register Lower (CTVL 1) Counter Timer Preset Register Lower (CTPL 1)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P77

SC28L202A1DGG,129

Mfr. #:
Buy SC28L202A1DGG,129
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 3-5V 2CH UART 3MBPS
Lifecycle:
New from this manufacturer.
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