Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
65
NOTES:
1. INTRN or OP3-OP7 when used as interrupt outputs.
2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching
signal, V
M
, to a point 0.2 V above V
OL
. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and
test environment are pronounced and can greatly affect the resultant measurement.
V
M
V
OL
+0.2 V
V
OL
WRN
INTERRUPT
1
OUTPUT
t
IR
V
M
V
OL
+0.2 V
V
OL
RDN
INTERRUPT
1
OUTPUT
t
IR
SD00735
Figure 11. Interrupt Timing (80xxx mode)
C1 = C2 ∼ 24 pF FOR C
L
= 13.5 pF. For the oscillator feedback loop the capacitors C1 and C2 are in series.
t
CLK
t
CTC
t
Rx
t
Tx
X1/SCLK
CTCLK
RxC
TxC
t
CLK
t
CTC
t
Rx
t
Tx
V
CC
470 Ω
X1/Sclk
X2*
CLK
*NOTE: X2 MUST BE LEFT OPEN.
X2
14.7456 MHz
X1
C1
C2
SC28L202
NOTE:
RESISTOR REQUIRED
FOR TTL INPUT.
TO UART
CIRCUIT
TYP.
160 kΩ
3 pF
3 pF
C1 and C2 should be chosen according to the crystal manufacturer’s specification.
C1 and C2 values will include any parasitic capacitance of the wiring and X1 X2 pins.
2pF
4pF
Package capacitance approximately 4 pF.
SD00736
PARASITIC CAPACITANCE
PARASITIC CAPACITANCE
Figure 12. Clock Timing
