Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
16
The modes of control are described in MR3[3:2]
00 = Host mode
01 = Auto transmit
10 = Auto Receive
11 = Auto receive and transmit
Mode control
Xon/Xoff mode control is accomplished via the MR3[3:2].
00 Xon/Xoff processing disabled. The host will control Rx, Tx.
01 Auto Tx control. Tx is stopped/started when Xoff/Xon is
received.
10 Auto Rx control. Receiver commands Tx to send Xoff at
trigger level.
11 Auto Rx and Tx control. Receiver commands Tx to send
Xoff as the receiver fills and commands the Tx to send
Xon when Rx FIFO fill level is lowered. This results in total
automatic control. No processor interrupt is required.
Note that MR3[7] controls the stripping of Xoff/Xon characters.
0 Xon/Xoff characters are sent to the Rx FIFO
1 Xon/Xoff characters are discarded.
The MR3[7] functions regardless of the setting of MR3[3:2]. This
allows for general purpose character recognition and processing.
(See ‘Character Stripping’.)
Xon Xoff Characters
The programming of these characters is usually done individually.
The standard Xon/Xoff characters are . Xon is 0x11, Xoff 0x13. Any
enabling of the Xon/Xoff functions will use the contents of the Xon
and Xoff character registers as the basis on which recognition is
predicated.
Host mode
When neither the auto-receiver or auto-transmitter modes are set,
the Xon/Xoff logic is operating in the host mode. In host mode, all
activity of the Xon/Xoff logic is initiated by commands to the CRx.
The Xoff command forces the transmitter to disable exactly as
though a Xoff character had been received by the RxFIFO. The
transmitter will remain disabled until the chip is reset or the CR (7:3)
= 10110 (Xoff resume) command is given. In particular, reception of
a Xon or disabling or re-enabling the transmitter will NOT cause
resumption of transmission. Redundant CRTXxx commands, i.e.
CRTXon, CRTXon, are harmless, although they waste time. A
CRTXon may be used to cancel a CRTXoff (and vice versa) but both
may be transmitted depending on the command timing with respect
to that of the transmitter state machine.
Auto-transmitter mode
When a channel receiver loads a Xoff character into the RxFIFO, the
channel transmitter will finish transmission of the current character
and then stop transmitting. A transmitter so idled can be restarted by
the receipt of a Xon character by the receiver or by a hardware or
software reset. The last option results in the loss of the
untransmitted contents of the TxFIFO. When operating in this mode
the Command Register commands for the transmitter are not
effective.
While idle data may be written to the TxFIFO and it continue to
present its fill level to the interrupt arbiter and maintains the integrity
of its status registers.
Use of ’00’ as a Xon/Xoff character is complicated by the Receiver
break operation which loads a ’00’ character on the RxFIFO. The
Xon/Xoff character detectors do not discriminate in this case from a
Xon/Xoff character received through the RxD pin.
NOTE: To be recognized as a Xon or Xoff character, the receiver
must have room in the RxFIFO to accommodate the character. An
Xon/Xoff character that is received resulting in a receiver overrun
does not effect the transmitter nor is it loaded into the RxFIFO,
regardless of the state of the Xon/Xoff transparency bit, MR3[7].
Receiver Mode
Since the receiving FIFO resources in the Dual UART are limited,
some means of controlling a remote transmitter is desirable in order
to lessen the probability of receiver overrun. The Dual UART
provides two methods of controlling the data flow. There is a
hardware-assisted means of accomplishing control, the so-called
out-of-band flow control, and an in-band flow control method.
The out-of-band flow control is implemented through the
CTSN–RTSN signaling via the I/O ports. The operation of these
hardware handshake signals is described in the receiver and
transmitter discussions.
In-band flow control is a protocol for controlling a remote transmitter
by embedding special characters within the message stream, itself.
Two characters, Xon and Xoff, which do not represent normal
printable character take on flow control definitions when the
Xon/Xoff capability is enabled. Flow control characters received may
be used to gate the channel transmitter on and off. This activity is
referred to as Auto-transmitter mode. To protect the channel receiver
from overrun, fixed fill levels (hardware set at 240 characters) of the
RxFIFO may be employed to automatically insert Xon/Xoff
characters in the transmitter’s data stream. This mode of operation
is referred to as auto-receiver mode. Commands issued by the host
CPU via the CR can simulate all these conditions.
Auto Receive and Transmit
This is a combination of both modes.
NOTE: Xon /Xoff characters
The Xon/Xoff character with errors will be accepted as valid. The
user has the option sending or not sending these characters to the
FIFO. Error bits associated with Xon/Xoff will be stored normally to
the receiver FIFO.
The channel’s transmitter may be programmed to automatically
transmit a Xoff character without host CPU intervention when the
RxFIFO fill level exceeds a fixed limit (240). In this mode it will
transmit a Xon character when the RxFIFO level drops below a
second fixed limit (16). A character from the TxFIFO that has been
loaded into the TxD shift register will continue to transmit.
Character(s) in the TxFIFO that have not been loaded to the
transmitter shift register are unaffected by the Xon or Xoff
transmission. They will be transmitted after the Xon/Xoff activity
concludes.
If the fill level condition that initiates Xon activity negates before the
flow control character can begin transmission, the transmission of
the flow control character will not occur. That is, either of the
following sequences may be transmitted depending on the timing of
the FIFO level changes with respect to the normal character times:
Fix This
Character Xoff Xon Character
Character Character
Hardware keeps track of Xoff characters sent that are not rescinded
by a Xon. This logic is reset by writing MR3[3:2] to ‘00’. If the user
drops out of Auto-receiver mode while the XISR shows Xoff as the
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
17
last character sent the Xon/Xoff logic would not automatically send
the negating Xon.
The kill CRTX command (of the command register) can be used to
cleanly terminate any pending CRTX commands.
NOTE: In no case will a Xon/Xoff character transmission be aborted.
Once the character is loaded into the TX Shift Register, transmission
continues until completion or a chip reset or transmitter reset is
encountered. The kill CRTX command has no effect in either of the
Auto modes.
Xon/Xoff Interrupts
The Xon/Xoff logic generates interrupts only in response to
recognizing either of the characters in the XonCR or XoffCR (Xon or
Xoff Character Registers). The transmitter activity initiated by the
Xon/Xoff logic or any CR command does not generate an interrupt.
The character comparators operate regardless of the value in
MR3[3:2]. Hence the comparators may be used as general-purpose
character detectors by setting MR3[3:2]= ‘00’ and enabling the
Xon/Xoff interrupt in the IMR.
The Dual UART can present the Xon/Xoff recognition event to the
interrupt arbiter for IRQN generation. The IRQN generation may be
masked by setting bit 4 of the Interrupt Mask Register, IMR. The bid
level of a Xon/Xoff recognition event is controlled by the Bidding
Control Register X, BCRx, of the channel. The interrupt status can
be examined in ISR[4]. If cleared, no Xon/Xoff recognition event is
interrupting. If set, a Xon or Xoff recognition event has been
detected. The X Interrupt Status Register, XISR, can be read for
details of the interrupt and to examine other, non-interrupting, status
of the Xon/Xoff logic. Refer to the XISR in the Register Descriptions.
The character recognition function and the associated interrupt
generation is disabled on hardware or software reset.
Multi-drop or Wake up or 9 bit mode
This mode is used to address a particular UART among a group
connected to the same serial data source. Normally it is
accomplished by redefining the meaning of the parity bit such that it
indicates a character as address or data. While this method is fully
supported in the SC28L202 it also supports recognition of the
character itself. Upon recognition of its address the receiver will be
enabled and data loaded onto the RxFIFO.
Further the Address recognition has the ability, if so programmed, to
disable (not reset) the receiver when an address is seen that is not
recognized as its own. The particular features of ‘Auto Wake and
Auto Doze’ are described in the detail descriptions under ‘Receiver
Operation’ above.
NOTE: Care should be taken in the programming of the character
recognition registers. Programming x’00, for example, may result in
a break condition being recognized as a control character. This will
be further complicated when binary data is being processed.
PROGRAMMING THE HOST INTERFACE
The SC28L202 is designed for a very close compatibility with legacy
software written for other Philips/Signetics 2 channel UARTs. The
part will initialize to the SC28L92 function. This function is controlled
in the low 16 address positions.
A reset (both hardware and software) will return the part to this
mode with the control registers set for 9600 baud, 8 bits, no parity
and one stop bit. Interrupt will be set for Receiver Ready and
transmitter Empty. Transmitters and receivers will not be enabled.
Basic operation should be obtained by a single write of 0xE0 to the
command register. That will enable the receiver and transmitter.
Addressing outside of the lower 16 address spaces will enable all
the advanced features. In general, before calling legacy code,
advanced features should be disabled (character stripping, for
example).
Writing control words into the appropriate registers programs the
operation of the DUART. Operational feedback is provided via status
registers that can be read by the CPU. The addressing of the
registers is described in the Register Map.
The contents of certain control registers are initialized to zero on
RESET. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Each channel has 3 mode registers (MR0, 1, 2) which control the
basic configuration of the channel. Mode, command, clock select,
and status registers are duplicated for each channel to provide total
independent operation and control. Refer to Table 2 for register bit
descriptions.
Philips Semiconductors Product data sheet
SC28L202Dual UART
2005 Nov 01
18
REGISTER DESCRIPTION AND PROGRAMMING
NOTE
Programmers may use either of two register sets or mix the features
of each. It is suggested that only the extended register set be used
in new designs. However if a system needed to use a block of
communications code written for an older system then that code
could merely be called. This is similar to calling a DOS
program in
a WINDOWS
environment. Before calling legacy code it is
recommended (but not required) to execute ‘Reset to C92’
command. Also consideration must be given to the I/O pins to avoid
contention of drivers of the pins and an external driver.
Two control register descriptions and maps are implemented in the
SC28L92: one represents the previous 4-bit address and the other
the new 7-bit address space representing the all the new features of
the new design.
The Design of the SC28L202 allows for high degree with former
Philips two channel communications controllers—DUARTs.
To facilitate this feature the complete register function and control of
the SC26C92 is replicated in the SC28L202. That is code written for
the SCN2681, SCN68681, SCC2692, SCC68692 and SC26C92 will
operate with this device.
With the execution of code written for previous DUARTs and
immediately after a hardware reset or a ‘Reset to C92’ command the
following configuration will exist:
1. The size of all FIFOs is set to 8 bytes (for legacy code).
2. FIFO interrupt levels are controlled by the bits of the MR
registers
3. All I/O ports are set to input.
4. Receiver FIFO set to interrupt on FIFO ready.
5. Transmitter FIFO set to interrupt on FIFO empty.
6. Baud selection follows previous 4 bit programming and baud rate
grouping controlled by the MR and ACR registers.
Table 2. SC28L202 REGISTER BIT DESCRIPTIONS
Registers that control Global Properties of the 28L202
GCCR – Global Configuration Control Register
THIS IS A VERY IMPORTANT REGISTER! IT SHOULD BE THE FIRST REGISTER ADDRESSED DURING INITIALIZATION.
Hex
Bit [7:6] Bit [5:3] Bit [2:1] BIT 0
Addr DACKN Assertion Reserved IVC Interrupt Vector Control ISR Read Mode
00 = 2 – 3 Sclk
01 = 1 – 2 Sclk
10 = 1/2 – 1 Sclk
11 = Reserved
Set to 0
00 = no interrupt vector
01 = IVR[7:0]
10 = IVR[7:1] + channel code
11 = IVR[7:5] + interrupt type + channel code
0 = ISR Unmasked
1 = ISR Read Masked by IMR
GCCR(7:6) DACKN Assertion
Motorola bus cycle time can be controlled by selecting a DACKN
assertion time based on X1/Sclk speed. The time programmed
should not be less than the minimum read or write pulse width.
See examples below.
X1/SCLK
#SCLK Cycles Delay
3.6864 MHz 1/2–1 136–272 ns
7.3728 MHz 1/2–1 68–136 ns
14.7456 MHz 1/2–1 34–68 ns
29.4912 MHz 1–2 34–68 ns
33.1776 MHz 2–3 60–90 ns
44.2368 MHz 2–3 46–68 ns
GCCR(5:3): Reserved
GCCR(2:1): Interrupt vector configuration
The IVC field controls if and how the assertion of IACKN (the
interrupt acknowledge pin) will form the interrupt vector for the
DUART. If b’00, no vector will be presented during an IACKN cycle.
The bus will be driven high (0xFF). If the field contains a b’01, the
contents of the IVR, Interrupt Vector Register, will be presented as
the interrupt vector without modification.
If IVC = 0x10, the channel code will replace the LSB of the IVR; if
IVC = b’11 then a modified interrupt type and channel code replace
the 3 LSBs of the IVR. NOTE: The modified type field IVR[2:1] is:
10 Receiver w/o error
11 Receiver with error
01 Transmitter
00 All remaining sources
GCCR(0): Interrupt Status Masking
This bit controls the readout mode of the Interrupt Status Register,
ISR. If set, the ISR reads the current status masked by the IMR, i.e.
only interrupt sources enabled in the IMR can ever show a ‘1’ in the
ISR. If cleared, the ISR shows the current status of the interrupt
source without regard to the Interrupt Mask setting.

SC28L202A1DGG,129

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 3-5V 2CH UART 3MBPS
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New from this manufacturer.
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