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STLC5046

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
August 2009 Doc ID 7052 Rev 5 1/51
1
STLC5046
Programmable four channel CODEC and filter
Features
■ Programmable monolithic 4 channel
■ CODEC/Filter
■ Single +3.3 V supply
■ Pin-strap / MCU control mode
■ A/µ Law programmable
■ Linear coding (16 bits) option
■ PCM highway format automatically detected:
1.536 or 1.544 MHz; 2.048, 4.096, 8192 MHz
■ TX gain programming: 16 dB range;
<0.1 dB step
■ RX gain programming: 26 dB range;
<0.1 dB step
■ Programmable time slot assignment
■ Digital and analog loopbacks
■ SLIC control port
■ Static mode (16 I/Os)
■ Dynamic mode (12 I/Os + 4 CS)
■ LQFP64 package
■ PCM in HI-Z mode
Description
The STLC5046 is a monolithic programmable 4
channel codec and filter. It operates with a single
+3.3 V supply.
The analog interface is based on a receive output
buffer driving the SLIC RX input and on an
amplifier input stage.
Due to the single supply voltage a proper mid
supply reference level is generated internally by
the device and all analog signals are referred to
this level (AGND).
The PCM interface uses one common 8 kHz
frame sync. pulse for transmit and receive
direction. The bit clock can be selected between
four standards: 1.536/1.544 MHz, 2.048 MHz,
4.096 MHz, 8192 MHz. Device programmability is
achieved by means of 41 registers allowing to set
the different parameters like TX/RX gains,
encoding Law (A/µ), time slot assignment,
independent channels power up/down,
loopbacks, PCM bits offset.
Thanks to pin-strap option, the most significant of
the above parameters can be set by hardware
connection of dedicated pins. This allow to use
this device also on line card without MCU on
board. When pin-strap option is selected different
pins of the device will change their function (see
pin description).
In MCU control mode the STLC5046 can be
programmed via serial interface running up to
4MHz.
One interrupt output pin is also provided.
Table 1. Device summary
LQFP64
Order code Temperature range Package Packing
E-STLC5046
(1)
1. ECOPACK
®
(see Section 7)
-40°C to +85°CLQFP64 Tube
www.st.com
Contents STLC5046
2/51 Doc ID 7052 Rev 5
Contents
1 Block diagram and pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Power on initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Power down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 PCM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.1 MCU mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.2 Pin-strap mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6 Control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7 SLIC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Registers addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1 Configuration register (CONF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.2 I/O Direction register (DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.3 I/O Data register channel #0 (DATA0) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.4 I/O Data register channel #1 (DATA1) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.5 I/O Data register channel #2 (DATA2) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.6 I/O Data register channel #3 (DATA3) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.7 Transmit Gain channel #0 (GTX0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.8 Transmit Gain channel #1 (GTX1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.9 Transmit Gain channel #2 (GTX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.10 Transmit Gain channel #3 (GTX3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.11 Receive Gain channel #0 (GRX0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.12 Receive Gain channel #1 (GRX1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.13 Receive Gain channel #2 (GRX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.14 Receive Gain channel #3 (GRX3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.15 Transmit Time Slot channel #0 (DXA0) . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.16 Transmit Time Slot channel#1 (DXA1) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.17 Transmit Time Slot channel #2 (DXA2) . . . . . . . . . . . . . . . . . . . . . . . . . 29
STLC5046 Contents
Doc ID 7052 Rev 5 3/51
3.1.18 Transmit Time Slot channel #3 (DXA3) . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.19 Receive Time Slot channel #0 (DRA0) . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.20 Receive Time Slot channel #1 (DRA1) . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.21 Receive Time Slot channel #2 (DRA2) . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.22 Receive Time Slot channel #3 (DRA3) . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.23 PCM Shift register (PCMSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.24 Interrupt Mask register for I/O port (DMASK) . . . . . . . . . . . . . . . . . . . . 33
3.1.25 Interrupt Mask register for CD port (CMASK) . . . . . . . . . . . . . . . . . . . . 34
3.1.26 Persistency Check register (PCHK-A/B) . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.27 Interrupt register (INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1.28 Alarm register (ALARM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1.29 Interrupt Mask register for Alarm (AMASK) . . . . . . . . . . . . . . . . . . . . . . 37
3.1.30 Loopback register (LOOPB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1.31 Transmit Preamplifier Gain register (TXG) . . . . . . . . . . . . . . . . . . . . . . . 37
3.1.32 Receive Amplifier Gain registers (RXG-10/32) . . . . . . . . . . . . . . . . . . . 39
3.1.33 Silicon Revision Identification Code (SR=D) . . . . . . . . . . . . . . . . . . . . . 39
4 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6 Transmission characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

STLC5046

Mfr. #:
Buy STLC5046
Manufacturer:
STMicroelectronics
Description:
Interface - CODECs Prog 4-Ch CODEC/Filt
Lifecycle:
New from this manufacturer.
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