STLC5046 Registers addresses
Doc ID 7052 Rev 5 27/51
00h:Stop any received signal, AGND level is forced on the VFRO3 analog output.
>00h:Digital gain is inserted in the TX path equal to:
20log[0.25+0.75*(progr. value/256)]
Pin-strap values:
GR3=1: -0.8 dB gain (value = E2h):
GR3=0: -4.3 dB gain (value = AFh):
Overall gain including also RXG:
GR3 = 1:-0.8 dB; GR3 = 0: -4.3 dB
3.1.15 Transmit Time Slot channel #0 (DXA0)
Addr=13h; Reset Value=00h
EN0=0: Selected transmit time slot on DX output is in H.I.
EN0=1: Selected transmit time slot on DX output is active carrying out the PCM encoded
signal of VFXI0.
T06..0: Define time slot number (0 to 127) on which PCM encoded signal of VFXI0 is carried
out.
If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows:
the 8 most significative bits in the programmed time slot, the 8 least significative bits in the
following timeslot.
Example: if T06..T00=00:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
11100010
10101111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EN0 T06 T05 T04 T03 T02 T01 T00
TS0 TS1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
