STLC5046 Datasheet STLC5046 | P16-P18

Functional description STLC5046

16/51 Doc ID 7052 Rev 5

Finally by means of the LOOPB register is possible to implement a digital or analog

loop_back on any of the selected channels.

TSX

represent the Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in

high impedance state except when a time slot is active on the DX output. In this case TSX

output pulls low to enable the backplane line driver. Should be strapped to VSS when not

used.

R/W = 0: Write register

R/W

= 1: Read register

D/S

= 0: Single byte

D/S

= 1: Two bytes

A5..A0: Register Address

2.6 Control interface

STLC5046 has two control modes, a microprocessor control mode and a pin-strap control

mode. The two modes are selected by M0 and M1 pins. When M0 = low, M1 = high (MCU

control mode) the MCU port is activated; and the 41 registers of the device can be

programmed. When M0 = high, M1 = low (Pin-strap mode) the microprocessor control port

is disabled and some of the digital pins change their function allowing to perform a very

basic programming of the device.

In pin-strap mode the status of the control pins is entered at power-on reset and refreshed at

any Frame Sync. cycle.

In MCU mode the control information is written to or read from STLC5046 via the serial four

wires control bus:

CCLK: Control Clock

: Chip Select input

CI: Serial Data input

CO: Serial Data output

All control instructions require 2 bytes, with the exception of the single byte for command

synchronization. The first byte specify the register address, and the type of access (Read or

Write). The second byte contain the data to be loaded into the register (on CI wire) or

carried out the register content (on CO wire) depending on the R/W bit of the first byte. CO

wire is normally in High Impedance and goes to low impedance only during the second byte

in case of Read operation. This allows to use a common wire for both CI/CO.

Serial data CI is shifted to the serial input register on the rising edge of CCLK and CO is

shifted out on the falling.

Table 4. Control byte structure

First byte (address)

7 6 5 4 3 2 1 0

R/W D/S A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

STLC5046 Functional description

Doc ID 7052 Rev 5 17/51

CS, normally High, is set Low during the transmission / reception of a byte, lasting 8CCLK

pulses.

Though, in general, two bytes of the same instruction take two CS

separated cycles,

STLC5046 can handle the data transfer in a single 16 CCLK CS cycle, in both the directions.

One additional wire provided to the control interface is an open drain interrupt output (INT)

that goes low when a change of status is detected on the I/O pins.

2.7 SLIC control interface

The device provides 12 I/O pins plus 4 CS signals. The interface can work in dynamic or

static mode: it can be selected by means of DIR register.

● Dynamic Mode: the I/O pins are configured as input or output by means of DIR register.

The CS signals are used to select the different SLIC interface. In this case the I/O pin

can be multiplexed. The data loaded from SLIC#n via I/O pins configured as input can

be read in the DATAn register. The data written in a DATAn register will be loaded on the

I/O pins configured as output when the Csn signal will be active.

● Static Mode: The CS signal can be used as I/O pins. They can be configured as input

or output I/O by means of DATA1 register. The data corresponding to the CS signal can

be read or written by means of DATA2 register. All data related to th other I/O pins can

be read or written by means of DATA0 register.

Registers addresses STLC5046

18/51 Doc ID 7052 Rev 5

3 Registers addresses

Table 5. Registers addresses (only MCU mode)

Address Name Description

00h CONF Configuration register

01h DIR-L I/O Direction (bit 7-0)

02h DIR-H I/O Direction (bit 11-8)

03h DATA0-L I/O Data ch#0/ Static Data; (bit 7-0)

04h DATA0-H I/O Data ch#0/ Static Data; (bit 11-8)

05h DATA1-L I/O Data ch#1 (bit 7-0) / CS Direction

06h DATA1-H I/O Data ch#1 (bit 11-8)

07h DATA2-L I/O Data ch#2 (bit 7-0) / CS Data

08h DATA2-H I/O Data ch#2 (bit 11-8)

09h DATA3-L I/O Data ch#3 (bit 7-0)

0Ah DATA3-H I/O Data ch#3 (bit 11-8)

0Bh GTX0 Transmit Gain ch#0

0Ch GTX1 Transmit Gain ch#1

0Dh GTX2 Transmit Gain ch#2

0Eh GTX3 Transmit Gain ch#3

0Fh GRX0 Receive Gain ch#0

10h GRX1 Receive Gain ch#1

11h GRX2 Receive Gain ch#2

12h GRX3 Receive Gain ch#3

13h DXA0 Transmit Timeslot ch#0

14h DXA1 Transmit Timeslot ch#1

15h DXA2 Transmit Timeslot ch#2

16h DXA3 Transmit Timeslot ch#3

17h DRA0 Receive Timeslot ch#0

18h DRA1 Receive Timeslot ch#1

19h DRA2 Receive Timeslot ch#2

1Ah DRA3 Receive Timeslot ch#3

1Bh PCMSH PCM Shift register

1Ch DMASK-L Interrupt Mask I/O Port (03h)

1Dh DMASK-H Interrupt Mask I/O Port (04h)

1Eh CMASK Interrupt Mask I/O Port (07h)

1Fh PCHK-A Persistency Check Time for Input A

20h PCHK-B Persistency Check Time for Input B

21h INT Interrupt register

22h ALARM Alarm register

23h AMASK Interrupt Mask for Alarm

24h LOOPB Loopback register

25h TXG Transmit Preamp. Gain

26h RXG-1,0 Receive Preamp. Gain (ch1 ch0)

27h RXG-3,2 Receive Preamp. Gain (ch3 ch2)

31h SRID Silicon Revision Identification Code

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51

STLC5046

Mfr. #:

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STMicroelectronics

Description:

Interface - CODECs Prog 4-Ch CODEC/Filt

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