Electrical characteristics STLC5046
42/51 Doc ID 7052 Rev 5
PCM interface timing
t
HMF
Hold time MCLK low to FS low 10 ns
t
SFM
Setup time, FS high to MCLK low 10 ns
t
DMD
Delay time, MCLK high to data
valid
10 ns
t
DMZ
(2)
Delay time, MCLK low to DX
disabled
Pull up resistor = 1 kΩ
C
load
= 30 pF
540ns
t
SDM
Setup time, D
R
valid to MCLK low 15 ns
t
HMD
Hold time, MCLK low to D
R
invalid 5 ns
t
DZC
(2)
Delay time, MCLK low to TSX
high
Pull up resistor = 1 kΩ
C
load
= 30 pF
40 ns
t
XDP
Delay time, MCLK high to TSX
low
10 ns
Serial control port timing
f
CCLK
Frequency of CCLK 4.096 MHz
t
WCH
Period of CCLK high Measured from V
IH
to V
IH
100 ns
t
WCL
Period of CCLK low Measured from V
IL
to V
IL
100 ns
t
RC
Rise time of CCLK Measured from V
IL
to V
IH
20 ns
t
FC
Fall time of CCLK Measured from V
IH
to V
IL
20 ns
t
HCS
Hold time, CCLK high to CS– low 5 ns
t
SSC
Setup time, CS– low to CCLK
high
10 ns
t
SDC
Setup time, CI valid to CCLK high 20 10 ns
t
HCD
Hold time, CCLK high to CI invalid 10 ns
t
DCD
Delay time, CCLK low to CO data
valid
30 ns
t
DSD
Delay time, CS–low to CO data
valid
20 ns
t
DDZ
(2)
Delay time CS–high or 8th CCLK
low to CO high impedance
whichever comes first
Pull up resistor = 1 kΩ
C
load
= 30 pF
50 ns
t
HSC
Hold time, 8th CCLK high to CS–
high
10 ns
t
SCS
Setup time, CS– high to CCLK
high
10 ns
Table 6. Electrical characteristics (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
