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STLC5046

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
Registers addresses STLC5046
34/51 Doc ID 7052 Rev 5
MD11..0=1: The corresponding I/O doesn’t generate interrupt.
MD11..0=0: The corresponding I/O (programmed as Input) generate interrupt if a change of
status is detected.
Input lines with persistency check generate interrupt if the changed status remains stable
longer than the time programmed in the persistency check registers PCHKA/B. Lines
without persistence check generate an immediate interrupt request.
Mask register has no effect on those pins configured as outputs, those pins will not generate
interrupt.
Pin-strap value.
3.1.25 Interrupt Mask register for CD port (CMASK)
Addr=1Eh; Reset Value=XFh
In MCU mode, dynamic I/O configuration, MCn bits are the disable/enable interrupt related
to the channel n:
MC3..0= 0 Any I/O line of the related channel is enabled to generate interrupt depending on
DMASK setting.
MC3..0=1 Any I/O line of the related channel is disabled to generate interrupt independently
of DMASK setting.
In MCU mode, static I/O configuration, MCn bits are the interrupt mask bits related to CSn
that are configured as I/O lines.
MC3..0=1: The corresponding I/O doesn’t generate interrupt.
MC3..0=0: The corresponding I/O generate interrupt if a change of status is detected.
Input lines with persistency check generate interrupt if the changed status remains stable
longer than the time programmed in the persistency check registers PCHKA/B
Lines without persistency check generate an immediate interrupt request.
Mask register has no effect on those pins configured as outputs, those pins will not generate
interrupt.
MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0
MD11 MD10 MD9 MD8
11111111
1111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MC3 MC2 MC1 MC0
STLC5046 Registers addresses
Doc ID 7052 Rev 5 35/51
Pin-strap value (value=00h):
3.1.26 Persistency Check register (PCHK-A/B)
Two input signals per channel, labeled A and B, are submitted to persistency check.
In dynamic mode (STA=0), A and B inputs of the four channels, are sampled on the
multiplexed lines IO0 (pin13) and IO1 (pin14).
In static mode (STA=1) the persistency check is performed on four pairs of lines, assigned to
each channel according to the table:
Addr=1Fh; Reset Value=00h
Addr=20h; Reset Value=00h
TA7..0 and TB7..0, content of PCHKA and PCHKB registers, define the minimum duration of
input A and B to generate interrupt; spurious transitions shorter than the programmed value
are ignored.
The time width can be calculated according to the formula:
Time-Width A = (TA7..0) x 64 µs
Time-Width B = (TB7..0) x 64 µs
If PCHKA/B is programmed to 00h the persistency check is not performed and any detected
transition will generate interrupt.
All the inputs, with or without persistency check, are sampled with a repetition rate of 32µs
Pin-strap value:
11111111
CHAN# Input A Input B
0 IO0 (pin 19) IO1 (pin 20)
1 IO4 (pin 17) IO5 (pin 18)
2 IO6 (pin 48) IO7 (pin 47)
3 IO10 (pin 44) IO11 (pin 43)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0
TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0
00000000
Registers addresses STLC5046
36/51 Doc ID 7052 Rev 5
3.1.27 Interrupt register (INT)
Addr=21h; Reset Value=00h
ICKF = 1: If interrupt is generated by a change of bit 0 in register ALARM.
In dynamic I/O configuration the ID3..0 bits latch the interrupt request from the related
channel.
Any single bit IDn is cleared after reading related I/O register or by setting MCn bit High (i.e.
when channel n is disabled to generate interrupt).
In static I/O configuration ID0 and ID2 bits latch the interrupt request from I/O11..0 and
CS3..0 respectively:
ID0: is set High when the interrupt is requested from any the I/O11..0 lines.
ID2: is set High when the interrupt is requested from any of the CS3..0 (configured as I/O).
ID0 and ID2 are cleared after reading related I/O register.
ID1 and ID3 are don’t care.
Pin-strap value (value=00b):
3.1.28 Alarm register (ALARM)
Addr=22h; Reset Value=00h
CKF=1: If number of PCM clock pulses in one frame period does not match expected value.
POR=1: If a Power On Reset is detected during operation.
The register ALARM is cleared after reading operation only if signals are inactive.
Pin-strap value (value=00h):
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ICKF ID3 ID2 ID1 ID0
00000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
POR CKF
00
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

STLC5046

Mfr. #:
Buy STLC5046
Manufacturer:
STMicroelectronics
Description:
Interface - CODECs Prog 4-Ch CODEC/Filt
Lifecycle:
New from this manufacturer.
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