STLC5046 Electrical characteristics
Doc ID 7052 Rev 5 43/51
Figure 8. Pin-strap mode short frame sync. timing
SLIC control interface timing
TCS Chip select repetition rate 31.25 µs
t
csw
Chip select pulse width 3.90 µs
t
DIV
Time CS low to data input valid 1.65 µs
t
DII
Time data input invalid to CS high 1.65 µs
t
DOA
Time data output available to CS
low
1.8 µs
t
DON
Time CS high to data output not
available
1.8 µs
1. All the digital input are five-volt tolerant
- maximum DC voltage 5.5 V
- maximum peak voltage 6.5 V
2. It is defined as the time at which the output achieves the off state.
Table 6. Electrical characteristics (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
12345671617
t
HMF
MCLK
t
RM
t
FM
t
WMH
t
WML
t
SFM
t
WFH
1234567 16
t
DMD
t
XDP
FS
TSX
DX
t
DMZ
t
DZC
1234567 16
t
SDM
t
HMD
DR
D98TL386C
Note: T
WFH
has to be shorter than or equal to 3 MCLK period to select Short Frame.
